7480 Group and 7481 Group User's Manual
1-55
HARDWARE
1.11 Interrupts
Figure 1.11.13 Setting of Interrupts (2)
b7
b0
b7
b0
0
00
0 0
0
0 00
0
b7
b0
0
b7
b0
b7
b0
1 11
11
1
1 11
1
When timer X interrupt is set, timer X interrupt is enabled.
Interrupt control register 1 (ICON1) [Address 00FE16]
Interrupt control register 2 (ICON2) [Address 00FF16]
When timer Y interrupt is set, timer Y interrupt is enabled.
When timer 1 interrupt is set, timer 1 interrupt is enabled.
When timer 2 interrupt is set, timer 2 interrupt is enabled.
When serial I/O receive interrupt is set, serial I/O receive interrupt is enabled.
When serial I/O transmit interrupt is set, serial I/O transmit interrupt is enabled.
When bus arbitration interrupt is set, bus arbitration interrupt is enabled.
When A-D conversion completion interrupt is set, A-D conversion completion interrupt is enabled.
When INT0 interrupt is set, INT0 interrupt is enabled.
When INT1 interrupt is set, INT1 interrupt is enabled.
When CNTR0 interrupt is set, CNTR0 interrupt is enabled.
When CNTR1 interrupt is set, CNTR1 interrupt is enabled.
Procedure 5 Using interrupt enable bit to ‘1’ (enabled)
When timer X interrupt is set, there is no timer X interrupt request.
Interrupt request register 1 (IREQ1) [Address 00FC16]
Interrupt request register 2 (IREQ2) [Address 00FD16]
When timer Y interrupt is set, there is no timer Y interrupt request.
When timer 1 interrupt is set, there is no timer 1 interrupt request.
When timer 2 interrupt is set, there is no timer 2 interrupt request.
When serial I/O receive interrupt is set, there is no serial I/O receive interrupt request.
When serial I/O transmit interrupt is set, there is no serial I/O transmit interrupt request.
When bus arbitration interrupt is set, there is no bus arbitration interrupt request.
When A-D conversion completion interrupt is set, there is no A-D conversion completion interrupt request.
When INT0 interrupt is set, there is no INT0 interrupt request.
When INT1 interrupt is set, there is no INT1 interrupt request.
When CNTR0 interrupt is set, there is no CNTR0 interrupt request.
When CNTR1 interrupt is set, there is no CNTR1 interrupt request.
Procedure 4 Setting using interrupt request bit to ‘0’ (no interrupt request)
Interrupt enabled
Processor status register (PS)
Procedure 6 Setting b2 of PS to ‘0’ when the interrupt disable flag is set to ‘1’ in procedure 1.
Procedure 7 Operate the function associated with each interrupt
When key-on wakeup interrupt is used:
System is set to enter the stop mode/wait mode with the STP/WIT instruction.
When timer interrupt is used:
Timer count start
When serial I/O receive interrupt, serial I/O transmit interrupt and bus arbitration interrupt are used:
Data is written to the transmit buffer register and transmit/receive start.
When A-D conversion completion interrupt is used:
Setting A-D control register (A-D conversion start)
Note: For details, refer to setting of each function.