參數(shù)資料
型號(hào)： M37471M2-XXXSP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁(yè)數(shù)： 7/49頁(yè)
文件大小： 601K
代理商： M37471M2-XXXSP
12
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 5 Interrupt control
Fig. 4 Structure of registers related to interrupt
b7
b0
Edge polarity selection register (EG)
(Address 00D416)
INT0 edge selection bit
INT1 edge selection bit
CNTR0 edge selection bit
CNTR1 edge selection bit
0 : Falling edge
1 : Rising edge
CNTR0/CNTR1 interrupt selection bit
0 : CNTR0
1 : CNTR1
INT1 source selection bit (at power-down state)
0 : P31/INT1
1 : P00–P07 “L” level (for key-on wake-up)
Nothing is allocated (The value is undefined at reading)
b7
b0
Interrupt request register 1
(Address 00FC16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
Nothing is allocated
(The value is undefined at reading)
Serial I/O transmit interrupt request bit
A-D conversion completion interrupt request bit
b7
b0
Interrupt control register 1
(Address 00FE16)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
Nothing is allocated
(The value is undefined at reading)
Serial I/O receive interrupt enable bit
A-D conversion completion interrupt enable bit
b7
b0
Interrupt request register 2
(Address 00FD16)
INT0 interrupt request bit
INT1 interrupt request bit
Nothing is allocated
(The value is undefined at reading)
CNTR0 or CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt requested
b7
b0
Interrupt control register 2
(Address 00FF16)
INT0 interrupt enable bit
INT1 interrupt enable bit
Nothing is allocated
(The value is undefined at reading)
CNTR0 or CNTR1 interrupt enable bit
0 : Interrupt disable
1 : Interrupt enabled
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
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