參數(shù)資料
型號(hào): M37274EFSP
廠商: Mitsubishi Electric Corporation
英文描述: CONN HEADER 14POS SGL PCB 30GOLD
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 51/147頁
文件大?。?/td> 2042K
代理商: M37274EFSP
51
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
Fig. 48. Sync Pulse Counter Register
(12) Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal V
sep
as a count source.
The count value in a certain time (T time) generated by f(X
IN
)/2
13
or
f(X
IN
)/2
13
is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F
16
,”
“1F
16
” is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter
register (address 020F
16
). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 02EA
16
).
Figure 48 shows the structure of the sync pulse counter and Figure
49 shows the synchronous signal counter block diagram.
Fig. 49. Synchronous Signal Counter Block Diagram
Reset
5-bit counter
Latch (5 bits)
f(X
IN
)/2
13
Composite
sync signal
H
SYNC
signal
Counter
Sync pulse
counter register
Data bus
Selection gate : connected to black
colored side when
reset.
b5
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (SYC) [Address 020F
16
]
R W
Sync Pulse Counter Register
0
to
4
0
R —
6, 7
0
R —
Count value
(SYC0 to SYC4)
5
0
R W
Count source (SYC5)
0: H
SYNC
signal
1: Composite sync signal
B
After reset
Functions
Name
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
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