參數(shù)資料
型號: M37273MFH
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 15/130頁
文件大?。?/td> 1663K
代理商: M37273MFH
14
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273MFH
XXXSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
I
S
F
R
1
A
r
e
a
(
a
d
d
r
e
s
s
e
s
C
0
1
6
t
o
B
D
F
1
6
)
D
D
D2
16
D
3
1
D
4
1
D
5
1
D
6
1
D
7
1
D8
16
D
9
1
D
A
1
D
B
1
DC
16
D
D
1
D
E
1
D
F
1
0
1
1
1
6
6
6
6
6
6
6
6
6
6
6
6
6
C0
16
C
1
1
C
2
1
C
3
1
C
4
1
C5
16
C
6
1
C
7
1
C8
16
C9
16
C
A
1
6
6
6
6
6
6
CB
16
C
C
1
C
D
1
C
E
1
C
F
1
6
6
6
6
6
A
d
d
r
e
s
o
P
s
P
O
P
o
S
o
r
t
D
r
t
P
p
P
5
o
6
(
r
(
P
t
P
5
c
6
)
Caption data register 3 (CD3)
Caption data register 4 (CD4)
O
D
c
o
n
t
r
o
l
r
e
H
r
i
z
o
n
t
a
l
p
o
s
i
Block control register 1 (BC1)
Block control register 2 (BC2)
Vertical position register 1 (VP1)
Vertical position register 2 (VP2)
W
i
n
d
o
w
r
e
g
i
s
t
e
r
W
i
n
d
o
w
r
e
g
i
s
t
e
r
I/O polarity control register (PC)
Raster color register (RC)
S
o
g
t
i
o
s
t
e
r
e
(
g
O
i
C
s
)
P
P
Port P2 (P2)
Port P2 direction register (D2)
o
o
r
r
t
t
P
P
1
1
(
d
P
i
1
r
e
)
c
t
i
o
n
r
e
g
i
s
t
e
r
(
D
1
)
Port P3 (P3)
Port P3 direction register (D3)
R
e
g
i
s
t
e
r
P
o
r
r
t
t
P
P
0
0
(
d
P
i
0
r
e
)
c
t
i
o
n
r
e
g
i
s
t
e
r
(
D
0
)
i
n
r
t
e
r
(
H
P
)
1
2
(
(
W
W
N
N
1
2
)
)
I
n
t
e
r
r
u
p
t
i
n
p
u
t
p
o
l
a
r
i
t
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
R
E
)
b
7
b0
Bit allocation
State immediately after reset
b7
b0
o
)
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
F
)
: “0” immediately after reset
:
I
n
a
d
t
e
e
t
e
r
r
m
s
i
n
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
f
r
e
e
0
1
<
S
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
>
: “1” immediately after reset
: Fix this bit to “0”
(do not write “1”)
:
<
i
t
a
l
l
o
c
a
t
i
o
n
>
F
u
n
c
t
i
o
n
b
i
t
:
N
o
f
u
n
c
t
i
o
n
b
i
t
: Fix this bit to “1”
(do not write “0”)
Name
:
1
0
00
16
00
16
00
16
0
00
16
0
0
0
0
0
P
F
2
P
F
3
PF4
PF5
P
F
7
IN
T
1
IN
T
2
IN
T
3
P30
P
3
1
P
3
0
D
P
3
1
D
P30C
T
3
S
C
P31C
00
16
00
16
00
16
00
16
40
16
00
16
OC4
O
C
5
O
C
2
O
C
3
O
C
0
O
C
1
OC6
P
B
C
1
0
B
C
1
1
BC12
C
BC13
BC14
BC15
C
P
P
N
N
BC16
BC17
C
B
C
2
0
B
C
2
1
B
2
2
BC23
P
P
BC24
P
P
B
2
5
BC26
B
2
7
VP10
V
P
1
1
VP12
V
1
3
V
1
4
V
1
5
VP16
VP17
VP20
N
N
V
P
2
1
VP22
V
2
3
V
2
4
V
2
5
VP26
N
N
C
VP27
W
1
0
WN11
WN12
WN13
WN14
W
1
5
W
1
6
WN17
W
2
0
WN21
WN22
WN23
WN24
W
2
5
W
2
6
WN27
0
RC0
RC1
RC2
RC7
0
0
0
R
C
3
RC4
0
1
0
1
0
1
6
6
CDL20
CDL21
CDL22
D
H
CDL23
D
H
CDL24
D
H
CDL25
D
H
CDL26
D
H
CDL27
CDH20
CDH21
C
2
2
C
2
3
C
2
4
C
2
5
C
2
6
CDH27
HP4
HP5
HP2
HP3
HP0
HP1
H
6
PC4
PC5
PC2
PC3
PC0
PC1
P
6
00
16
00
16
00
16
0
0
6
Fig. 8.2.2 Memory Map of Special Function Register 1 (SFR1) (1)
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