參數(shù)資料
型號: M37273MFH-052SP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 107/130頁
文件大小: 1663K
代理商: M37273MFH-052SP
106
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273MFH–XXXSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
F
F
F
F
F
F
F6
16
F7
16
F
F9
16
F
F
F
F
F
FF
16
0
1
1
1
2
1
3
1
4
1
5
1
6
6
6
6
6
6
8
1
6
A
1
B
1
C
1
D
1
E
1
6
6
6
6
6
E
E
E
E
E
E
E6
16
E
E8
16
E9
16
E
0
1
1
1
2
1
3
1
4
1
5
1
6
6
6
6
6
6
7
1
6
E
EC
16
E
EE
16
E
F
1
B
1
6
D
1
6
6
A
1
6
A
d
d
r
e
s
a
D
s
Serial I/O register (SIO)
S
r
i
a
l
I
/
O
m
A
A
-
-
D
D
c
c
o
o
n
n
t
t
r
r
o
o
l
l
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
A
A
D
D
1
2
)
)
Timer 5 (T5)
T
m
e
r
T
m
e
r
Timer 2 (T2)
T
m
e
r
T
m
e
r
T
m
e
r
T
m
e
r
I
2
C
d
a
I
2
C
a
d
i
i
6
1
(
(
T
T
6
1
)
)
C
C
a
a
p
p
t
t
i
i
o
o
n
n
d
d
a
a
t
t
a
a
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
C
C
D
D
1
2
)
)
C
Data slicer test register 2
D
t
a
s
l
i
c
e
r
t
e
Synchronous signal counter register (HC)
a
p
t
i
o
n
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
(
C
P
S
)
Clock run-in detect register (CRD)
Data clock position register (DPS)
R
e
g
i
s
t
e
r
D
a
t
t
a
a
s
s
l
l
i
i
c
c
e
e
r
r
c
c
o
o
n
n
t
t
r
r
o
o
l
l
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
D
D
S
S
C
C
1
2
)
)
i
i
i
i
3
4
m
m
(
(
o
o
T
T
d
d
3
4
e
e
)
)
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
T
T
M
M
1
2
)
)
t
d
a
e
s
h
s
i
f
t
r
r
e
e
g
g
i
i
s
t
t
e
r
r
(
S
S
0
0
D
)
I
2
C
I
2
C
C
U
c
c
o
l
o
m
n
c
t
r
k
o
d
l
o
r
e
n
r
e
g
t
r
g
i
o
i
s
t
l
e
r
t
e
r
e
r
g
(
S
i
s
(
C
1
t
P
D
e
)
c
e
r
U
(
M
S
2
)
)
Interrupt request register 1 (IREQ1)
In
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
e
g
g
g
i
i
i
s
s
s
t
t
t
e
e
e
r
r
r
1
2
2
(
(
(
I
I
I
C
C
R
E
O
O
Q
N
N
2
1
2
)
)
)
a
s
t
r
e
g
i
s
t
e
r
1
P
o
s
b7
b0
B
i
t
a
l
l
o
c
a
t
i
o
n
State immediately after reset
b7
b0
I
S
F
R
1
A
r
e
a
(
a
d
d
r
e
s
s
e
s
E
0
1
6
t
o
F
F
1
6
)
e
o
d
e
r
e
g
i
s
t
e
r
(
S
M
)
I
2
C
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
1
)
r
s
s
e
(
)
:
:
0
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
:
I
n
a
d
t
e
e
t
e
r
r
m
s
i
n
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
f
r
e
e
0
1
<State immediately after reset>
1
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
:
:
F
(
F
(
i
x
o
t
n
h
i
s
t
b
w
i
r
t
i
t
t
o
e
0
1
)
d
o
:
<
B
i
t
a
l
l
o
c
a
t
i
o
n
>
F
u
n
c
t
i
o
n
b
i
t
: No function bit
i
x
o
t
n
h
i
s
t
b
w
i
r
t
i
t
t
o
e
1
0
)
d
o
N
a
m
e
:
1
0
T
M
2
0
T
M
2
1
T
M
2
2
T
M
2
3
T
M
2
4
T
M
1
0
T
M
1
1
T
M
1
2
T
M
1
3
T
M
1
4
CM2
T
IN
M
IN
M
1
R
T
S
M
M
2
R
TM3R
T
M
4
R
O
IN
S
D
R
V
S
C
R
IN3R
M
5
CK0
2
1
R
D
R
S1R
T
1
E
T
2
E
TM3E
T
M
4
E
O
IN
S
D
E
V
S
C
E
1
E
D
S
E
S1E
2
E
T
M
2
5
00
16
FF
16
0
0
7
1
F
1
7
1
0
1
6
6
6
0
FF
16
7
1
6
T
M
1
5
T
M
M
1
6
TM17
M
T
2
6
T
2
7
S
A
D
0
SAD1
S
A
D
2
S
A
D
3
S
A
D
4
SAD5
SAD6
R
B
W
LRB
C
C
0
AD0
C
C
0
AAS
AL
S
PIN
BB
TRX
MST
B
0
B
1
BC2
C
E
O
ALS
BSEL0
BSEL1
C
R
0
C
R
1
C
R
2
C
C
1
R
3
C
C
1
R
4
ACK
1
0
1
6
0
00
16
3
0
1
C
1
6
C
K
R
R
IICR
T
6
R
IN3E
M
5
C
K
E
IICE
T
6
E
T
M
5
6
C
CM7
C
M
5
C
M
6
SM0
D
C
SM1
D
C
SM2
SM3
A
1
0
A
1
1
ADC12
A
D
C
1
4
ADC20
ADC21
ADC22
ADC25
SM5
SM6
ADC24 ADC23
1
0
S
FAST
MODE
B
A
I
D
T
00
16
0
0
1
6
0
1
6
D
S
C
1
0
DSC11
1
D
L
D
S
C
1
2
DSC20
D
L
DSC23
D
DSC24
D
DSC25
D
L
C
R
D
3
C
R
D
4
C
R
D
5
C
R
D
6
C
R
D
7
D
P
S
3
D
P
S
4
D
P
S
5
D
P
S
6
DPS7
C
P
S
0
C
P
S
3
C
P
S
4
C
P
S
5
C
P
S
1
CPS2
C
P
S
6
CPS7
H
C
0
H
C
3
H
C
4
H
C
5
H
C
1
HC2
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
6
C
D
H
1
0
CDH13
C
D
H
1
4
C
D
H
1
5
CDH11
C
D
H
1
2
C
D
H
1
6
C
D
H
1
7
C
1
0
C
L
1
3
C
L
1
4
C
1
5
C
1
1
CDL12
C
D
L
1
6
CDL17
00
16
0
1
6
0
1
6
0
1
6
0
1
6
6
00
16
0
1
0
1
6
6
0
1
6
D
1
D2
D
3
D4
D5
D
6
D
7
D0
0
0
0
0
0
0
0
0
0
0
0
0
ACK
BIT
9
1
6
6
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