參數(shù)資料
型號(hào)： M37273M8-204SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 22/130頁
文件大小： 1663K
代理商： M37273M8-204SP
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273MFH
–
XXXSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
Fig. 8.3.4 Interrupt Control Register 1
b7b6 b
5b
4b
3 b
2b
1b
0
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
I
C
O
N
1
)
[
A
d
d
r
e
s
s
0
0
F
E
1
6
]
B
0
Name
F
n
I
n
I
n
:
I
:
I
:
I
0
:
1
:
u
t
t
t
n
t
n
t
n
t
I
n
t
I
n
t
n
r
r
r
r
r
r
r
r
c
r
u
r
u
r
u
r
u
r
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r
u
r
u
t
i
o
t
t
t
t
t
t
t
t
n
d
e
d
e
d
e
d
e
s
i
n
i
n
i
n
i
n
A
f
t
e
r
r
e
s
e
t
R W
R W
In
t
e
r
r
u
p
t
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
1
Timer 1 interrupt
enable bit (TM1E)
Timer 2 interrupt
enable bit (TM2E)
Timer 3 interrupt
enable bit (TM3E)
Timer 4 interrupt
enable bit (TM4E)
0
1
0
1
0
1
:
:
:
I
e
e
e
e
e
e
e
e
p
p
p
p
p
p
p
p
s
a
a
s
a
a
s
a
a
s
a
a
b
b
b
b
b
b
b
b
l
e
l
e
l
e
l
e
l
e
l
e
l
e
e
d
d
d
d
d
d
d
d
l
1
2
3
4
OSD interrupt enable bit
(OSDE)
V
SYNC
interrupt enable
bit (VSCE)
INT3 external interrupt
enable bit (IN3E)
0
1
0
1
0
1
:
:
:
:
:
:
I
I
I
I
I
I
n
n
n
n
n
n
t
t
t
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t
e
e
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e
r
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r
r
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r
u
u
u
u
u
u
p
p
p
p
p
p
t
t
t
t
t
t
d
e
d
e
d
e
i
n
i
s
n
i
s
n
s
a
a
a
a
a
a
b
b
b
b
b
b
l
e
l
e
l
e
l
e
l
e
e
d
d
d
d
d
d
l
0
0
0
0
0
0
R W
R W
R W
R W
R —
7
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
5
0
R W
6
0
R W
Fig. 8.3.5 Interrupt Control Register 2
b7b6 b
5b
4b
3 b
2b
1b
0
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
I
C
O
N
2
)
[
A
d
d
r
e
s
s
0
0
F
F
1
6
]
B
0
Name
F
t
e
t
e
t
e
t
e
t
e
t
e
t
e
t
e
u
n
I
n
I
n
:
I
n
:
I
n
1
:
I
n
0
:
I
n
1
:
I
n
n
r
r
r
r
r
r
r
r
c
u
u
u
u
u
u
u
u
t
i
o
t
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t
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t
t
t
n
d
e
d
e
d
e
d
e
s
i
s
n
i
s
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i
s
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i
s
n
A
f
t
e
r
r
e
s
e
t
R W
R W
In
t
e
r
r
u
p
t
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
2
INT1 external interrupt
enable bit (IN1E)
Data slicer interrupt
enable bit (DSE)
Serial I/O interrupt
enable bit (S1E)
f(X
IN
)/4096 interrupt
enable bit (CKE)
0
1
0
1
0
:
:
:
I
r
r
r
r
r
r
r
r
p
p
p
p
p
p
p
p
a
a
a
a
a
a
a
a
b
b
b
b
b
b
b
b
l
e
l
e
l
e
l
e
l
e
l
e
l
e
e
d
d
d
d
d
d
d
d
l
1
2
3
4
INT2 external interrupt
enable bit (IN2E)
Multi-master I
2
C-BUS
interface interrupt enable
bit (IICE)
Timer 5 6 interrupt
enable bit (TM56E)
0
1
0
1
1
1
:
:
:
:
I
I
I
I
n
n
n
n
t
t
t
t
e
e
e
e
r
r
r
r
r
r
r
r
u
u
u
u
p
p
p
p
t
t
t
t
d
e
d
e
i
n
i
s
n
s
a
a
a
a
b
b
b
b
l
e
l
e
l
e
e
d
d
d
d
l
0
0
0
0
0
R W
R W
R W
R W
5
0
R W
6
0
:
:
I
I
n
n
t
t
e
e
r
r
r
r
u
u
p
p
t
t
d
e
i
n
s
a
a
b
b
l
e
e
d
d
l
0
R W
7
Timer 5 6 interrupt
switch bit (TM56C)
0
:
:
T
T
i
i
m
m
e
e
r
r
5
6
0
R W
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