參數(shù)資料
型號: M37221M6-054SP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
中文描述: 單芯片8位CMOS微機電壓合成
文件頁數(shù): 18/61頁
文件大?。?/td> 1386K
代理商: M37221M6-054SP
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
18
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
φ
= 4 MHz)
Table 2. Multi-master I
2
C-BUS interface functions
MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a circuit for serial communica-
tions conformed with the Philips I
2
C-BUS data transfer format. This
interface, having an arbitration lost detection function and a synchro-
nous function, is useful for serial communications of the multi-mas-
ter.
Figure 12 shows a block diagram of the multi-master I
2
C-BUS inter-
face and Table 2 shows multi-master I
2
C-BUS interface functions.
This multi-master I
2
C-BUS interface consists of the I
2
C address reg-
ister, the I
2
C data shift register, the I
2
C clock control register, the I
2
C
control register, the I
2
C status register and other control circuits.
Item
Format
Communication mode
SCL clock frequency
φ
System clock = f(X
IN
)/2
Note:
We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con-
trol function (bits 6 and 7 of the I
2
C control register at address
00DA
16
) for connections between the I
2
C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
Fig. 12. Block diagram of multimaster I
2
C-BUS interface
I
2
C address register
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Noise
elimination
circuit
Serial
data
(SDA)
Address comparator
I
2
C data shift register
b7
b0
Data
control
circuit
AL
circuit
I
2
C clock control register
System clock (
φ
)
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
MST TRX BB
PIN
AL AAS AD0 LRB
b0
I
2
C status
register
S1
Internal data bus
b7
b0
BSEL1 BSEL0
10BIT
SAD
ALS ESO BC2
BC1
BC0
S1D
I
2
C control register
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
b7
b0
ACK
ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1CCR0
Clock division
S0
S2
S0D
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