參數(shù)資料
型號(hào)： M37221EFSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)電壓合成與屏幕顯示控制器
文件頁(yè)數(shù)： 21/61頁(yè)
文件大?。?/td> 1386K
代理商： M37221EFSP
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
21
(5) I
2
C Status Register
The I
2
C status register (address 00D9
16
) controls the I
2
C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
I
Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit
is set to “1.” Except in the ACK mode, the last bit value of received
data is input. The state of this bit is changed from “1” to “0” by execut-
ing a write instruction to the I
2
C data shift register (address 00D7
16
).
I
Bit 1: General call detecting flag (AD0)
This bit is set to “1” when a general call
8
whose address data is all “0”
is received in the slave mode. By a general call of the master device,
every slave device receives control data after the general call. The
AD0 bit is set to “0” by detecting the STOP condition or START con-
dition.
8
General call:The master transmits the general call address “00
16
”
to all slaves.
I
Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-order
7 bits of the I
2
C address register (address 00D8
16
).
A general call is received.
In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
When the address data is compared with the I
2
C address
register (8 bits consisted of slave address and RBW), the first
bytes agree.
The state of this bit is changed from “1” to “0” by executing a write
instruction to the I
2
C data shift register (address 00D7
16
).
Fig. 15. Connection port control by BSEL0 and BSEL1
Fig. 16. Structure of I
2
C control register
“0”
“1” BSEL0
SCL1/P1
1
SCL2/P1
2
“0”
“1” BSEL1
“0”
“1” BSEL0
SDA1/P1
3
SDA2/P1
4
“0”
“1” BSEL1
Multi-master
I
2
C-BUS
interface
SCL
SDA
7
BSEL1 BSEL0SAD
ALS
ES0
BC2
BC1
BC0
0
Connection control bits
between I
2
C-BUS
interface and ports
b7
b6
Connection port
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1,
SCL2, SDA2
I
2
C control register
(S1D : address 00DA
16
)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0
0 : 8
0 0
1 : 7
0 1
0 : 6
0 1
1 : 5
1 0
0 : 4
1 0
1 : 3
1 1
0 : 2
1 1
1 : 1
I
2
C-BUS interface use
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
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