參數(shù)資料
型號(hào)： M37212M4
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述： 單芯片8位單片機(jī)（8位單片機(jī)）
文件頁數(shù)： 34/119頁
文件大小： 1308K
代理商： M37212M4
34
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
M37212M4/M8–XXXSP, M37212M6–XXXSP/FP
M37212EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
8.6.3 I
2
C Clock Control Register
The I
2
C clock control register (address 00DB
16
) is used to set ACK
control, SCL mode and SCL frequency.
(1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
(3) Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock
8
is generated. When
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
8
ACK clock: Clock for acknowledgement
Fig. 8.6.4 I
2
C Address Register
(4) Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit generated
by the data receiving device.
Note:
Do not write data into the I
2
C clock control register during transmission.
If data is written during transmission, the I
2
C clock generator is reset, so
that data cannot be transmitted normally.
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