參數(shù)資料
型號: M37212M4-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件頁數(shù): 19/119頁
文件大?。?/td> 1308K
代理商: M37212M4-XXXSP
115
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
M37212M4/M8–XXXSP, M37212M6–XXXSP/FP
M37212EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
Address 00FD16
Addresses 00FE16
b7b6 b5 b4b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address 00FD
BName
Functions
After reset RW
Interrupt Request Register 2
0
INT1 external interrupt
request bit (IT1R)
0 : No interrupt request issued
1 : Interrupt request issued
1
INT2 external interrupt
request bit (IT2R)
2
Serial I/O interrupt
request bit (S1R)
3
4
f(XIN)/4096 interrupt
request bit (MSR)
5, 6
7
Fix this bit to “0.”
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
V: “0” can be set by software, but “1” cannot be set.
0
V
0
V
0
V
0
V
0 : No interrupt request issued
1 : Interrupt request issued
16
]
R
R —
R W
0
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0R —
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
BNameFunctions
RW
Interrupt Control Register 1
0
Timer 1 interrupt
enable bit (TM1E)
0 : Interrupt disabled
1 : Interrupt enabled
1
Timer 2 interrupt
enable bit (TM2E)
2
Timer 3 interrupt
enable bit (TM3E)
3
4
OSD interrupt enable bit
(OSDE)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
R
7
Timer 4 interrupt
enable bit (TM4E)
0 : Interrupt disabled
1 : Interrupt enabled
5
VSYNC interrupt enable
bit (VSCE)
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
6
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
After reset
INT3 external interrupt
enable bit (IT3E)
Multi-master I2C-BUS interface
interrupt enable bit (IICE)
0 : Interrupt disabled
1 : Interrupt enabled
W
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相關代理商/技術參數(shù)
參數(shù)描述
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