42
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
M37212M4/M8–XXXSP, M37212M6–XXXSP/FP
M37212EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
Fig. 8.6.12 Address Data Communication Format
S
S
l
a
v
e
e
r
a
d
d
r
e
s
s
A
D
a
t
a
A
D
a
t
a
A
/
A
P
R
/
“0
r
t
W
7
b
t
r
i
a
t
s
n
”
1
a
d
t
t
o
a
8
t
o
b
a
i
t
s
s
1
c
e
t
e
o
i
8
e
r
b
i
t
s
S
S
l
a
v
e
e
r
a
d
d
r
e
s
s
A
D
a
t
a
A
D
a
t
a
A
P
7
b
r
e
i
t
c
s
e
“1
c
e
”
i
1
f
t
o
o
8
a
b
i
s
t
s
l
1
n
a
t
s
o
m
8
i
t
b
e
i
r
t
s
(1
)
A
m
a
s
t
-
s
m
i
t
t
e
r
a
n
s
m
i
t
s
l
a
v
e
-
r
v
S
S
1
l
a
t
v
7
e
e
r
b
a
i
d
t
s
d
r
e
s
s
s
A
A
D
a
t
a
7
b
t
r
i
a
t
s
n
“0
t
”
8
o
b
i
s
t
s
l
a
1
r
t
o
i
t
h
8
a
b
i
1
t
s
0
(2
)
A
m
a
s
t
-
i
v
e
r
r
e
v
e
s
d
a
t
a
r
m
a
v
e
-
t
r
t
S
2
l
a
d
v
e
b
y
a
t
d
e
d
r
e
s
s
n
A
D
a
t
a
A
/
A
P
1
d
t
e
o
8
s
b
i
t
s
S
S
1
l
a
t
v
7
e
e
r
b
a
i
d
t
s
d
r
e
s
s
s
A
A
7
b
r
e
i
t
c
s
e
“0
c
e
”
i
8
a
b
s
i
t
l
s
a
7
-
b
b
i
i
t
a
s
(3
)
A
m
a
s
t
-
s
m
i
t
t
e
r
r
a
n
s
m
i
t
s
d
a
t
a
t
a
v
e
-
r
e
c
e
i
v
e
w
-
b
i
t
a
d
r
s
S
2
l
a
d
v
e
b
y
a
t
d
e
d
r
e
s
s
n
D
a
t
a
1
t
o
8
b
i
t
s
S
r
S
1
l
a
t
v
7
e
b
a
i
d
t
s
d
r
e
s
s
s
A
D
a
t
a
A
P
1
t
o
8
b
i
t
s
“1
”
(4
)
A
m
a
s
t
-
i
v
e
r
r
e
v
e
s
d
a
t
a
f
r
o
m
v
e
-
t
r
a
n
s
m
i
t
t
e
r
w
i
t
h
a
1
0
t
d
d
r
e
s
s
S : S
A : A
S
r : R
T
C
e
A
K
s
R
t
a
T
i
r
t
c
o
n
d
i
t
i
o
n
P
R
/
:
W
S
T
:
O
R
P
e
c
d
o
/
n
W
d
r
i
i
t
t
i
e
o
n
b
b
t
a
i
t
c
o
n
d
i
t
i
o
n
F
F
r
r
o
o
m
m
m
s
a
a
s
v
t
e
e
r
t
t
o
m
s
a
l
a
s
v
t
e
e
r
l
o
R
/
W
R
/
W
R
/
W
R
/
W
8.6.12 Precautions when using multi-master
I
2
C-BUS interface
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I
2
C-BUS
interface are described below.
I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the START condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure us-
ing multi-master
Procedure example (The necessary conditions of the generating
procedure are described as the following
to
).
—
LDA
SEI
BBS 5,S1,BUSBUSY
BUSFREE:
STA S0
LDM #$F0, S1
CLI
(Taking out of slave address value)
(Interrupt disabled)
(BB flag confirming and branch process)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
BUSBUSY:
CLI
(Interrupt enabled)
Use “STA,” “STX” or “STY” of the zero page addressing instruction
for writing the slave address value to the I
2
C data shift register.
Use “LDM” instruction for setting trigger of START condition gener-
ating.
{
Write the slave address value of above
and set trigger of START
condition generating of above
continuously shown the above
procedure example.
Disable interrupts during the following three process steps:
BB flag confirming
Writing of slave address value
Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.