MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
5
PIN DESCRIPTION
Pin
V
CC
,
V
SS
CNV
SS
RESET
X
IN
X
OUT
φ
P0
0
– P0
7
P1
1
– P1
4
P1
5
– P1
7
P2
0
– P2
7
P3
0
, P3
1
P3
2
– P3
5
P4
0
, P4
1
P4
2
P6
0
– P6
3
OSC1,
OSC2
H
SYNC
V
SYNC
R, G, B,
OUT
D-A
Name
Power source voltage
CNV
SS
Reset input
Clock input
Clock output
Timing output
I/O port P0
I/O port P1
Input port P1
I/O port P2
I/O port P3
Input port P3
I/O port P4
Input port P4
Output port P6
Clock input for CRT
display
Clock output for CRT
display
H
SYNC
input
V
SYNC
input
CRT output
DA Output
Input /
Output
Input
Input
Output
Output
I/O
I/O
Input
I/O
I/O
Input
I/O
Input
Output
Input
Output
Input
Input
Output
Output
Functions
Apply voltage of 5V ± 10% to V
CC
, and 0V to V
SS
.
This is connected to V
SS
.
To enter the reset state, the reset input pin must be kept at a “L” for 2
μ
s or more (under nor-
mal V
CC
conditions).
If more time is needed for the crystal oscillator to stabilize, this “L” condition should be main-
tained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an exter-
nal ceramic resonator or a quartz-crystal oscillator is connected between the X
IN
and
X
OUT
pins. If an external clock is used, the clock source should be connected the X
IN
pin and
the X
OUT
pin should be left open.
This is the timing output pin.
Port P0 is an 8-bit I/O port with directional registers allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is CMOS output.
The output structure is N-channel open-drain output. When PWM4, PWM5, PWM6 and
PWM7 are used, P0
0
, P0
1
, P0
2
and P0
3
are in common with PWM output pins of PWM4,
PWM5, PWM6 and PWM7.
Ports P1
0
, P1
1
, P1
2
, P1
3
and P1
4
are 5-bit I/O ports and have basically the same functions
as port P0. The output structure is CMOS output.
Ports P1
5
, P1
6
and P1
7
are 3-bit input ports and they are in common with input pins of A-D
comparator (A-D1, A-D2 and A-D3).
Port P2 is an 8-bit I/O port and has basically the same functions as port P0.
The output structure is CMOS output.
Ports P3
0
and P3
1
are 2-bit I/O ports and have basically the same functions as port P0.
The output structure is CMOS output.
Ports P3
2
, P3
3
, P3
4
and P3
5
are 4-bit input ports and ports P3
2
and P3
3
are in common
with external clock input pins of timers 2 and 3. Ports P3
4
and P3
5
are in common with
external interrupt input pins INT1 and INT2. Port P3
5
is in common with an input pin of A-D
comparator (A-D4).
Ports P4
0
and P4
1
are 2-bit I/O ports and have basically the same functions as port P0.
When serial I/O is used, ports P4
0
and P4
1
are in common with S
OUT
pin and S
CLK
pin, re-
spectively.
Port P4
2
is an 1-bit Input port, and it is common with an input pin of A-D comparator (A-D5)
and serial input pin (S
IN
).
Port P6 is an 4-bit output port. The output structure is N-channel open-drain. This port is in
common with 6-bit PWM output pins PWM0-PWM3.
This is the I/O pins of the clock generating circuit for the CRT display function.
This is the horizontal synchronizing signal input for CRT display.
This is the vertical synchronizing signal input for CRT display.
This is a 4-bit output pin for CRT display. The output structure is CMOS output. This is in
common with port P5
2
– P5
5
.
This is an output pin for 14-bit PWM.