參數(shù)資料
型號： M37161M8-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù)： 66/129頁
文件大?。?/td> 1092K
代理商： M37161M8-XXXSP
Rev.1.00
2003.11.25
page 41 of 128
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
(3) RESTART condition generation procedure
Procedure example (The necessary conditions for the procedure
are described in to below.)
Execute the following procedure when the PIN bit is “0.”
LDM
#$00, S1
(Select slave receive mode)
LDA
—
(Take out slave address value)
SEI
(Interrupt disabled)
STA
S0
(Write slave address value)
LDM
#$F0, S1
(Trigger RESTART condition generating)
CLI
(Interrupt enabled)
Select the slave receive mode when the PIN bit is “0.” Do not write
“1” to the PIN bit. Neither “0” nor “1” is specified for the writing to
the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
The SCL pin is released by writing the slave address value to the
I2C data shift register. Use “STA,” “STX” or “STY” of the zero page
addressing instruction for writing.
Use “LDM” instruction for setting trigger of RESTART condition
generation.
Write the slave address value of and set trigger of RESTART
condition generation of continuously, as shown in the above pro-
cedure example.
Disable interrupts during the following two process steps:
Write of slave address value
Trigger RESTART condition generation
(4) STOP condition generation procedure
Procedure example (The necessary conditions for the procedure
are described in to below.)
SEI
(Interrupt disabled)
LDM #$C0, S1
(Select master transmit mode)
NOP
(Set NOP)
LDM #$D0, S1
(Trigger STOP condition generation)
CLI
(Interrupt enabled)
Write “0” to the PIN bit when master transmit mode is selected.
Execute “NOP” instruction after master transmit mode is set. Also,
set trigger of STOP condition generation within 10 cycles after se-
lecting the master trasmit mode.
Disable interrupts during the following two process steps:
Select master transmit mode
Trigger STOP condition generation
(5) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an
instruction to set the MST and TRX bits to “0” from “1” simultaneously
as it may cause the SCL pin the SDA pin to be released after about
one machine cycle. Also, do not execute an instruction to set the
MST and TRX bits to “0” from “1” when the PIN bit is “1,” as it may
cause the same problem.
(6) Process of after STOP condition generation
Do not write data in the I2C data shift register S0 and the I2C status
register S1 until the bus busy flag BB becomes “0” after generation
the STOP condition in the master mode. Doing so may cause the
STOP condition waveform from being generated normally. Reading
the registers does not cause the same problem.
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參數(shù)描述
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