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參數(shù)資料
| 型號： | M37150M8-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 93/142頁 |
| 文件大?。?/td> | 1712K |
| 代理商： | M37150M8-XXXFP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37150M6/M8/MA/MC/MF-XXXFP, M37150EFFP
53
Rev. 1.0
8.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CVIN pin. The low-pass filter attenuates the noise
of the clamped composite video signal. The CVIN pin to which com-
posite video signal is input requires an external capacitor (0.1
F)
coupling. Pull down the CVIN pin with a resistor of hundreds of kilo-
ohms to 1 M
. In addition, we recommend installing a simple low-
pass filter externally, using a resistor and a capacitor at the CVIN pin
(refer to Figure 8.10.1).
8.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
8.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
(1) Horizontal Synchronous Signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
(2) Vertical Synchronous Signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 4 of data slicer control regis-
ter 2 (address 00E116).
Method 1
The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this LOW level.
Method 2
The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync sig-
nal exits or not in the LOW level period of the timing
signal immediately after this LOW level. If a falling
exists, a Vsep signal is generated in synchronization
with the rising of the timing signal (refer to Figure
8.10.6).
Figure 8.10.6 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 8.10.7, when the A level matches the B level, this bit
is “0.” In the case of a mismatch, the bit is “1.”
Fig. 8.10.6 Vsep Generating Timing (method 2)
Composite s
Timing
signal
Vsep signal
Measure LOW period
A Vsep signal is generated at a rising of the timing signal
immediately after the LOW level width of the composite
sync signal exceeds a certain time.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37150MF-XXXFP | 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42 |
| M37150MC-XXXFP | 8-BIT, MROM, 8.95 MHz, MICROCONTROLLER, PDSO42 |
| M37151MC-XXXFP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42 |
| M37151MF-XXXFP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42 |
| M37151M6-XXXFP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37150MA | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150MA-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150MC | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150MC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150MF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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