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參數資料
| 型號： | M36W108ABZN |
| 廠商： | 意法半導體 |
| 英文描述： | 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product |
| 中文描述： | 8兆1兆× 8，啟動塊閃存和1兆位128KB的x8 SRAM的低電壓多媒體存儲產品 |
| 文件頁數： | 7/35頁 |
| 文件大?。?/td> | 247K |
| 代理商： | M36W108ABZN |
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M36W108T, M36W108B
Write.
Write operations are used to give Instruc-
tion Commands to the memory or to latch input
data to be programmed. A write operation is initi-
ated when Chip Enable (EF) is Low and Write En-
able (W) is at V
IL
with Output Enable (G) at V
IH
.
Addresses are latched on the falling edge of W or
EF whichever occurs last. Commands and Input
Data are latched on the rising edge of W or EF
whichever occurs first.
Output Disable.
The data outputs are high im-
pedance when the Output Enable (G) is at V
IH
with
Write Enable (W) at V
IH
.
Standby.
The memory is in standby when Chip
Enable (EF) is at V
IH
and the P/E.C. is idle. The
power consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable (G) or Write Enable (W) in-
puts.
Automatic Standby.
After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Instructions and Commands
Seven instructions are defined (see Table 7) to
perform Read Array, Auto Select (to read the Elec-
tronic Signature), Program, Block Erase, Chip
Erase, Erase Suspend and Erase Resume. The
internal P/E.C. automatically handles all timing
and verification of the Program and Erase opera-
tions. The Status Register Data Polling, Toggle,
Error bits and the RB output may be read at any
time, during programming or erase, to monitor the
progress of the operation.
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.).
The C.I. latches commands written to the memory.
Commands are made of address and data se-
quences. Two coded cycles unlock the Command
Interface. They are followed by an input command
or a confirmation command. The coded sequence
consists of writing the data AAh at the address
5555h during the first cycle and the data 55h at the
address 2AAAh during the second cycle.
Table 6. Flash User Bus Operations
(1)
Note: 1. X = V
IL
or V
IH
.
Table 7. Read Flash Electronic Signature
Operation
EF
G
W
RP
A0
A1
A6
A9
A12
A15
DQ0-DQ7
Read Byte
V
IL
V
IL
V
IH
V
IH
A0
A1
A6
A9
A12
A15
Data Output
Write Byte
V
IL
V
IH
V
IL
V
IH
A0
A1
A6
A9
A12
A15
Data Input
Output Disable
V
IL
V
IH
V
IH
V
IH
X
X
X
X
X
X
Hi-Z
Stand-by
V
IH
X
X
V
IH
X
X
X
X
X
X
Hi-Z
Reset
X
X
X
V
IL
X
X
X
X
X
X
Hi-Z
Code
Device
EF
G
W
A0
A1
Other
Addresses
DQ0-DQ7
Manufact. Code
V
IL
V
IL
V
IH
V
IL
V
IL
Don’t care
20h
Device Code
M36W108T
V
IL
V
IL
V
IH
V
IH
V
IL
Don’t care
D2h
M36W108B
V
IL
V
IL
V
IH
V
IH
V
IL
Don’t care
DCh
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