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參數(shù)資料
| 型號： | M36W0R6050T1ZAQE |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| 中文描述： | 64兆位（4兆】16日，多銀行，突發(fā)）閃存和32兆位（2字節(jié)】16）移動存儲芯片，多芯片封裝 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 159K |
| 代理商： | M36W0R6050T1ZAQE |
M36W0R6050T1, M36W0R6050B1
Signal descriptions
9/22
2
Signal descriptions
See
Figure 1: Logic diagram
and
Table 1: Signal names
, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A21)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components,
whereas A21 is an address input for the Flash memory component only. The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus
Write operations they control the commands sent to the Command Interface of the Flash
memory Program/Erase Controller, and they select the cells to access in the PSRAM.
2.2
Data inputs/outputs (DQ0-DQ15)
For the Flash memory, the Data I/O outputs the data stored at the selected address during a
Bus Read operation or inputs a command or the data to be programmed during a Write Bus
operation.
For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper
part of the selected address during a Write or Read operation, when Upper Byte Enable
(UB
P
) is driven Low.
Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the
selected address during a Write or Read operation, when Lower Byte Enable (LB
P
) is driven
Low.
2.3
Flash Chip Enable (E
F
)
The Chip Enable inputs activate the memory control logics, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V
IL
, and
Reset is High, V
IH
, the device is in
active mode. When Chip Enable is at V
IH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is reduced to the standby level.
2.4
Flash Output Enable (G
F
)
The Output Enable pins control data outputs during Flash memory Bus Read operations.
2.5
Flash Write Enable (W
F
)
The Write Enable controls the Bus Write operation of the Flash memories’ Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36W0R6050T1ZAQF | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| M36W0R6050T3 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP |
| M36W0R6050T3ZAQE | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP |
| M36W0R6050T3ZAQF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36W0R6050T4ZAQE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH PSRAM 96M |
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