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參數(shù)資料
| 型號(hào)： | M36W0R6050B1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| 中文描述： | 64兆位（4兆】16日，多銀行，突發(fā)）閃存和32兆位（2字節(jié)】16）移動(dòng)存儲(chǔ)芯片，多芯片封裝 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 159K |
| 代理商： | M36W0R6050B1 |
M36W0R6050T1, M36W0R6050B1
Signal descriptions
11/22
2.12
PSRAM Chip Enable (E2
P
)
When de-asserted (Low), the Chip Enable input E2
P
, puts the device in Power-Down mode.
This is the lowest power mode according to the Configuration Register settings (see
M69KB048BD datasheet).
2.13
PSRAM Output Enable (G
P
)
The Output Enable, G
P
, provides a high speed tri-state control, allowing fast read/write
cycles to be achieved with the common I/O data bus.
2.14
PSRAM Write Enable (W
P
)
The Write Enable, W
P
, controls the Bus Write operation of the memory’s Command
Interface.
2.15
PSRAM Upper Byte Enable (UB
P
)
The Upper Byte Enable, UB
P
, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16
PSRAM Lower Byte Enable (LB
P
)
The Lower Byte Enable, LB
P
, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17
V
DDF
supply voltage
V
DDF
provides the power supply to the internal core of the Flash memory component. It is
the main power supplies for all Flash memory operations (Read, Program and Erase).
2.18
V
DDP
supply voltage
The V
DDP
Supply Voltage supplies the power for all operations (Read or Write) and for
driving the refresh logic, even when the device is not being accessed.
2.19
V
DDQF
supply voltage
V
DDQF
provides the power supply for the Flash memory I/O pins. This allows all Outputs to
be powered independently of the Flash memory core power supply, V
DDF
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36W0R6050B1ZAQE | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| M36W0R6050B1ZAQF | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| M36W0R6050T1 | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| M36W0R6050T1ZAQE | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| M36W0R6050T1ZAQF | 64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36W0R6050B1ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| M36W0R6050B1ZAQF | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb 】16) PSRAM, multi-chip package |
| M36W0R6050B3 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP |
| M36W0R6050B3ZAQE | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP |
| M36W0R6050B3ZAQF | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP |
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