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參數(shù)資料
| 型號(hào)： | M368L6423FTN-CB3B0 |
| 廠(chǎng)商： | Sanken Electric Co.,Ltd. |
| 英文描述： | 184pin Unbuffered Module based on 256Mb F-die with 64/72-bit Non-ECC / ECC |
| 中文描述： | 184pin緩沖模塊，基于256Mb的F -死去64/72-bit非ECC / ECC的 |
| 文件頁(yè)數(shù)： | 14/19頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | M368L6423FTN-CB3B0 |
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DDR SDRAM
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Table 5 : Output Slew Rate Characteristice (X8 Devices only)
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Table 7 : Output Slew Rate Matching Ratio Characteristics
Delta Slew Rate
tDS
tDH
Units
Notes
+/- 0.0 V/ns
0
0
ps
i
+/- 0.25 V/ns
+50
+50
ps
i
+/- 0.5 V/ns
+100
+100
ps
i
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
1.0
4.5
a,c,d,f,g
Pulldown slew
1.2 ~ 2.5
1.0
4.5
b,c,d,f,g
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
0.7
5.0
a,c,d,f,g
Pulldown slew
1.2 ~ 2.5
0.7
5.0
b,c,d,f,g
AC CHARACTERISTICS
DDR466
PARAMETER
MIN
MAX
Notes
Output Slew Rate Matching Ratio (Pullup to Pulldown)
-
-
e,k
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR466 devices to ensure proper system perfor-
mance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 :
Input Slew Rate for DQ, DQS, and DM
Table 2
:
Input Setup & Hold Time Derating for Slew Rate
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
AC CHARACTERISTICS
DDR466
PARAMETER
SYMBOL
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
0.5
4.0
V/ns
a, k
Input Slew Rate
tIS
tIH
Units
Notes
0.5 V/ns
0
0
ps
h
0.4 V/ns
+50
0
ps
h
0.3 V/ns
+100
0
ps
h
Input Slew Rate
tDS
tDH
Units
Notes
0.5 V/ns
0
0
ps
j
0.4 V/ns
+75
+75
ps
j
0.3 V/ns
+150
+150
ps
j
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