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| 型號： | M368L1713CTL-LB3 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity |
| 中文描述： | 128MB DDR SDRAM的模組（16Mx64基于16Mx8 DDR內(nèi)存）緩沖184Pin DIMM插槽64位Non-ECC/Parity |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 83K |
| 代理商： | M368L1713CTL-LB3 |
184pin Unbuffered DDR SDRAM MODULE
M368L1713CTL
Rev. 0.3 May. 2002
8. I/O Setup/Hold Plateau Derating
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF
±
310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
tDS
tDH
(ns/V)
(ps)
(ps)
This derating table is used to increase t
DS
/t
DH
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
I/O Input Level
tDS
(ps)
tDH
(ps)
(mV)
±
280
+50
+50
Delta Rise/Fall Rate
0
0
0
±
0.25
±
0.5
+50
+50
+100
+100
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
tIH/tIS
(ps)
(ps)
CK slew rate
(Single ended)
tDSS/tDSH
tAC/tDQSCK
(ps)
tLZ(min)
(ps)
tHZ(max)
(ps)
1.0V/ns
0
0
0
0
0
0.75V/ns
+50
+50
+50
-50
+50
0.5V/ns
+100
+100
+100
-100
+100
<Reference>
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