- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383295 > M368L1713CTL-CB3 (SAMSUNG SEMICONDUCTOR CO. LTD.) 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity PDF資料下載
參數(shù)資料
| 型號： | M368L1713CTL-CB3 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity |
| 中文描述： | 128MB DDR SDRAM的模組（16Mx64基于16Mx8 DDR內(nèi)存）緩沖184Pin DIMM插槽64位Non-ECC/Parity |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 83K |
| 代理商： | M368L1713CTL-CB3 |
184pin Unbuffered DDR SDRAM MODULE
M368L1713CTL
Rev. 0.3 May. 2002
DDR SDRAM IDD spec table
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol
IDD0
IDD1
B3(DDR333@CL=2.5)
880
1120
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
760
1000
Unit
mA
mA
Notes
760
1000
IDD2P
IDD2F
IDD2Q
32
256
160
32
200
120
32
200
120
mA
mA
mA
IDD3P
IDD3N
320
440
240
440
240
440
mA
mA
IDD4R
IDD4W
IDD5
1280
1280
1680
1240
1240
1600
1240
1240
1600
mA
mA
mA
IDD6
Normal
Low power
IDD7A
16
8
16
8
2800
16
8
mA
mA
mA
Optional
3200
2800
(Vdd = 2.7V, T= 10’ C)
AC OPERATING CONDITIONS
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
0.7
0.5*VDDQ-0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V, V
DDQ
=2.5V, T
A
= 0 to 70
°
C
)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
1.5
V
Input Levels(VIH/VIL)
VREF+0.31/VREF-0.31
V
Input timing measurement reference level
VREF
V
Output timing measurement reference level
Vtt
V
Output load condition
See Load Circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M368L3313DTL | 256MB DDR SDRAM MODULE (32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM) |
| M368L3313DTL-CA2 | 256MB DDR SDRAM MODULE (32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM) |
| M368L3313DTL-CB0 | 256MB DDR SDRAM MODULE (32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM) |
| M368L3313DTL-CB3 | 256MB DDR SDRAM MODULE (32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM) |
| M368L6423ETM-CC5 | 184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M368L1713CTL-LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity |
| M368L1713CTL-LB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity |
| M368L1713CTL-LB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity |
| M368L2923BTM-CCC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II |
| M368L2923BTM-LCC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。