參數(shù)資料
型號(hào)： M368L1624DTL
廠(chǎng)商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
中文描述： 16Mx64 DDR SDRAM的184Pin DIMM插槽基礎(chǔ)上16Mx16顯示
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 354K
代理商： M368L1624DTL
DDR SDRAM
Rev. 1.2 May. 2003
128MB, 256MB, 512MB Unbuffered DIMM
AC Timing Parameters and Specifications
Parameter
Symbol
- CC(DDR400@CL=3)
Min
55
70
40
15
15
10
15
2
5
6
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.2
0.2
0.35
- C4(DDR400@CL=3)
Min
60
70
40
18
18
10
15
2
5
6
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.2
0.2
0.35
Unit
Note
Max
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Internal write to read command delay
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ps
tCK
tCK
tCK
tCK
70K
70K
Clock cycle time
CL=3.0
CL=2.5
tCK
10
12
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
10
12
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
16
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
Write preamble setup time
Write preamble
Write postamble
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tWPST
tDSS
tDSH
tDQSH
13
5
0.6
0.6
4
tCK
DQS-in low level width
Address and Control Input setup time
Address and Control Input hold time
tDQSL
tIS
tIH
0.35
0.6
0.35
0.6
tCK
ns
h,7~10
h,7~10
0.6
0.6
ns
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
Control & Address input pulse width for each input
tHZ
tLZ
tMRD
tDS
tDH
tDIPW
tIPW
-
tAC max
tAC max
-
tAC max
tAC max
ns
ns
tCK
ns
ns
ns
ns
us
us
3
3
tAC min
2
0.4
0.4
1.75
2.2
15.6
7.8
tHP
-tQHS
min
tCH/tCL
tAC min
2
0.4
0.4
1.75
2.2
15.6
7.8
tHP
-tQHS
min
tCH/tCL
i, j
i, j
9
9
Refresh interval time
Up to 128Mb
tREFI
6
256Mb, 512Mb, 1Gb
Output DQS valid window
tQH
-
-
ns
12
Clock half period
tHP
-
-
ns
11, 12
相關(guān)PDF資料
PDF描述
M368L1624DTL-C(L)A2 16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
M368L1624DTL-C(L)B0 16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
M368L1624DTL-C(L)B3 16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
M368L1624DTM-LCC 184pin Unbuffered Module based on 256Mb D-die 64/72-bit Non ECC/ECC
M368L1713CTL-LA2 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M368L1624DTL-C(L)A2 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
M368L1624DTL-C(L)B0 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
M368L1624DTL-C(L)B3 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
M368L1624DTL-CLA2 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
M368L1624DTL-CLB0 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*