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參數(shù)資料
| 型號： | M366S1723FTU-C7A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SDRAM Unbuffered Module |
| 中文描述： | 內(nèi)存緩沖模塊 |
| 文件頁數(shù)： | 16/26頁 |
| 文件大小： | 486K |
| 代理商： | M366S1723FTU-C7A |
64MB, 128MB, 256MB Unbuffered DIMM
Rev. 1.3 May 2004
SDRAM
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter
Symbol
7A
Unit
Note
Min
Max
CLK cycle
time
CAS latency=3
t
CC
7.5
1000
ns
1
CAS latency=2
10
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
ns
1,2
CAS latency=2
6
Output data
hold time
CAS latency=3
t
OH
3
ns
2
CAS latency=2
3
CLK high pulse width
t
CH
2.5
ns
3
CLK low pulse width
t
CL
2.5
ns
3
Input setup time
t
SS
1.5
ns
3
Input hold time
t
SH
0.8
ns
3
CLK to output in Low-Z
t
SLZ
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.4
ns
CAS latency=2
6
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