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參數(shù)資料
| 型號： | M35080-MN3T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 8 Kbit Serial SPI Bus EEPROM With Incremental Registers |
| 中文描述： | 8千位串行SPI總線的EEPROM與增量寄存器 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 139K |
| 代理商： | M35080-MN3T |
3/18
M35080
Figure 3. Data and Clock Timing
AI01438
C
C
MSB
LSB
CPHA
D or Q
0
1
CPOL
0
1
(though not to the WIP and WEL bits, which are
set or reset by the device’s internal logic).
Bit 7 of the status register (as shown in Table 4) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the level being
applied to the W input).
When bit 7 (SRWD) of the status register is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W:
– If W pin is high, it is possible to write to the sta-
tus register, after having set the WEL bit using
the WREN instruction (Write Enable Latch).
– If W pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EEPROM area, protected by
the BP1 and BP0 bits of the status register, are
also hardware protected against data corrup-
tion, and appear as a Read Only EEPROM area
for the microcontroller. This mode is called the
Hardware Protected Mode (HPM).
It is possible to enter the Hardware Protected
Mode (HPM) either by setting the SRWD bit after
pulling low the W pin, or by pulling low the W pin
after setting the SRWD bit.
The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W pin.
If W pin is permanently tied to the high level, the
Hardware Protected Mode is never activated, and
the memory device only allows the user to protect
a part of the memory, using the BP1 and BP0 bits
of the status register, in the Software Protected
Mode (SPM).
IMPORTANT:
if W pin is left floating, not driven by
the application, W is read as a logical ’0’.
Table 3. Write Protection Control
W
SRWD
Bit
Mode
Status Register
Data Bytes
Protected Area
Unprotected Area
0 or 1
0
Software
Protected
(SPM)
Writeable (if the WREN
instruction has set the
WEL bit)
Software write protected
by the BP0 and BP1 bits
of the status register
Writeable (if the WREN
instruction has set the
WEL bit)
1
1
0
1
Hardware
Protected
(HPM)
Hardware write protected
Hardware write protected
by the BP0 and BP1 bits
of the status register
Writeable (if the WREN
instruction has set the
WEL bit)
Table 4. Status Register Format
Note: 1. BP0, BP1: Read and write bits
2. UV, INC, WEL, WIP: Read only bits.
3. SRWD: Read and Write bit.
b7
b0
SRWD
UV
X
INC
BP1
BP0
WEL
WIP
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