- 您現(xiàn)在的位置：買賣IC網 > PDF目錄359055 > M34D64MN (意法半導體) 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory PDF資料下載
參數(shù)資料
| 型號： | M34D64MN |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| 中文描述： | 64/32千位串行IC總線EEPROM，帶有硬件寫控制記憶的熱門季 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 119K |
| 代理商： | M34D64MN |
7/15
M34D64, M34D32
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the
master sends another START condition, and
repeats the Device Select Code, with the RW bit
set to ‘1’. The memory acknowledges this, and
outputs the contents of the addressed byte. The
master must
not
acknowledge the byte output, and
terminates the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to 1. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as
an Ack polling sequence can be used by the
master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the WC pin.
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
AI01847
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
Send
Byte Address
First byte of instruction
with RW = 0 already
decoded by M24xxx
相關PDF資料 |
PDF描述 |
|---|---|
| M34D64RBNT5 | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64RBNT6 | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64WBNT5 | CAP 1500UF 35V ELECT LXY RAD |
| M34D64WBNT6 | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64MNT1 | GDEP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34D64MNT1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64MNT5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64MNT6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64-R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| M34D64RBNT1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復。