參數(shù)資料
型號: M34C02-LMB1TG
廠商: 意法半導(dǎo)體
英文描述: 2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
中文描述: 2千位串行IC總線的EEPROM內(nèi)存串行存在檢測
文件頁數(shù): 19/31頁
文件大?。?/td> 162K
代理商: M34C02-LMB1TG
M34C02-W, M34C02-L, M34C02-R
Use within a DRAM DIMM
19/31
4
Use within a DRAM DIMM
In the application, the M34C02-W, M34C02-L and M34C02-R are soldered directly in the
printed circuit module. The 3 Chip Enable inputs (pins 1, 2 and 3) are wired at V
CC
or V
SS
through the DIMM socket (see
Table 4
). The pull-up resistors needed for normal behavior of
the I
2
C bus are connected on the I
2
C bus of the mother-board (as shown in
Figure 11
).
The Write Control (WC) of the M34C02-W, M34C02-L and M34C02-R can be left
unconnected. However, connecting it to V
SS
is recommended, to maintain full read and write
access.
4.1
Programming the M34C02-W, M34C02-L and M34C02-R
When the device is delivered, full read and write access is given to the whole memory array.
It is recommended that the first step is to use the test equipment to write the module
information (such as its access speed, its size, its organization) to the first half of the
memory, starting from the first memory location. When the data has been validated, the test
equipment can send a Write command to the Protection Register, using the device select
code ’01100000b’ followed by an address and data byte (made up of Don’t Care values) as
shown in
Figure 6
. The first 128 bytes of the memory area are then write-protected, and the
M34C02-W, M34C02-L and M34C02-R will no longer respond to the specific device select
code ’0110000xb’. It is not possible to reverse this sequence.
Table 4.
DRAM DIMM Connections
DIMM Position
E2
E1
E0
0
V
SS
V
SS
V
SS
1
V
SS
V
SS
V
CC
2
V
SS
V
CC
V
SS
3
V
SS
V
CC
V
CC
4
V
CC
V
SS
V
SS
5
V
CC
V
SS
V
CC
6
V
CC
V
CC
V
SS
7
V
CC
V
CC
V
CC
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