參數(shù)資料
型號(hào)： M34C02-LDW1G
廠商： 意法半導(dǎo)體
英文描述： 2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
中文描述： 2千位串行IC總線的EEPROM內(nèi)存串行存在檢測(cè)
文件頁數(shù)： 17/31頁
文件大小： 162K
代理商： M34C02-LDW1G
M34C02-W, M34C02-L, M34C02-R
Device operation
17/31
3.8
Read Operations
Read operations are performed independently of whether hardware or software protection
has been set.
The device has an internal address counter which is incremented each time a byte is read.
3.8.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10
) but
without
sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the Device Select Code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not
acknowledge the byte, and terminates the transfer with a Stop condition.
3.8.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10
,
without
acknowledging the byte.
3.8.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master
does
acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must
not
acknowledge the last byte, and
must
generate a Stop
condition, as shown in
Figure 10
.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.8.4
Acknowledge in Read Mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9
th
bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Stand-by mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34C02-LDW1P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
M34C02-LDW1TG 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
M34C02-LDW1TP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
M34C02-LDW6G 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
M34C02-LDW6P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
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