
Rev.1.02
May 25, 2007
REJ03B0179-0102
4571 Group
Fig 5.
Port block diagram (3)
IAP3 instruction
OP3A instruction
(Note 1)
P30, P31(Note 2)
D
T
Q
Aj
Register A
Aj
(Note 3)
FR0j
(Note 3)
(Note 1)
(Note1)
C/CNTR1(Note 2)
D
T
Q
SCP instruction
RCP instruction
S
R
Q
PWMOD
Timer 1 underflow signal
W51
W12
Carrier wave output auto-control signal
PWMOUT
(Note 1)
K(Note 2)
Edge detection
circuit
Key-on wakeup input
K22
(Note 4)
Register A
A0
IAK instruction
Notes 1.
This symbol represents a parasitic diode on the port.
2.
Applied potential to these ports must be V DD or less.
3.
j represents bits 0 or 1.
4. Falling edge of port input is detected.