16
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V1
0
–V1
3
and V2
0
–V2
3
), and interrupt request
flags (EXF0, T1F, T2F, T3F) are “1.” The interrupt actually
occurs 2 to 3 machine cycles after the cycle in which all three
conditions are satisfied. The interrupt occurs after 3 machine
cycles only when the three interrupt conditions are satisfied
on execution of instructions other than one-cycle instructions
(Refer to Figure 16).
Fig. 16 Interrupt sequence
Notes 1: The system clock = f(X
IN
)/4 is selected just after system is released from reset.
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the instruction executed at the time when each
interrupt activated condition is satisfied.
2 to 3 machine cycles
(Notes 2, 3)
Software starts
from interrupt address.
Flag cleared
Interrupt enabled state
EI instruction
execution cycle
Interrupt enable
flag (INTE)
Retaining level for 4 cycles or
more of f(X
IN
) is necessary.
Interrupt disabled state
Flag
EXF0
Flag
T1F, T2F
T3F
INT pin
External
interrupt
Timer 1,
timer 2,
timer 3
interrupts
Interrupt activated
condition satisfied
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
3
1 machine cycle
f(X
IN
)
System clock=f(X
IN
)/4 selected
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
3
f(X
IN
)
System clock=f(X
IN
) selected
G
When an interrupt request flag is set after its interrupt is enabled (Note 1)
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