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參數(shù)資料
| 型號(hào)： | M3455AGCFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁(yè)數(shù)： | 8/148頁(yè) |
| 文件大?。?/td> | 1807K |
| 代理商： | M3455AGCFP |
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Rev.1.02
Nov 26, 2008
Page 105 of 146
REJ03B0224-0102
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB2
(Transfer data to Accumulator and register B from timer 2)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
0
111
00
01 2 27 1 16
11
-
Opera-
tion:
(B)
← (T27T24)
(A)
← (T23T20)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T27
T24) of timer 2 to reg-
ister B.
Transfers the low-order 4 bits (T23
T20) of timer 2 to regis-
ter A.
TABE
(Transfer data to Accumulator and register B from register E)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
0
010
10
10 2 02 A 16
11
-
Opera-
tion:
(B)
← (E7E4)
(A)
← (E3E0)
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E7
E4) of register E to reg-
ister B, and low-order 4 bits of register E to register A.
TABP p
(Transfer data to Accumulator and register B from Program memory in page p)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
00
10 p5 p4 p3 p2 p1 p0 2 0
8
+p
p 16
1
3
-
Opera-
tion:
(SP)
← (SP) + 1
(SK(SP))
← (PC)
(PCH)
← p
(PCL)
← (DR2DR0, A3A0)
(B)
← (ROM(PC))74
(A)
← (ROM(PC))30
(UPTF)
← 1
(DR1, DR0)
← (ROM(PC))9, 8
(DR2)
← 0
(PC)
← (SK(SP))
(SP)
← (SP) 1
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to
0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-
order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant
bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
p is 0 to 63 for M3455AG8, and p is 0 to 95 for M3455AGC.
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
TABPS
(Transfer data to Accumulator and register B from Pre-Scaler)
Instruc-
tion
code
D9
D0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
0
111
01
01 2 27 5 16
11
-
Opera-
tion:
(B)
← (TPS7TPS4)
(A)
← (TPS3TPS0)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M3455AGC-XXXFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| M3455AG8FP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| M3455AGC-XXXFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| M3455AG8-XXXFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| M34570MD-XXXFP | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO36 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3455AGC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M3455-SL001 | 制造商:Alpha Wire 功能描述: |
| M3455-SL002 | 制造商:Alpha Wire 功能描述: |
| M3455-SL005 | 制造商:Alpha Wire 功能描述: |
| M3455-SL199 | 制造商:Alpha Wire 功能描述: |
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