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參數(shù)資料
| 型號： | M34519M6-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 101/138頁 |
| 文件大?。?/td> | 1146K |
| 代理商： | M34519M6-XXXFP |
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4519 Group
Rev.3.01
2005.06.15
page 63 of 160
REJ03B0007-0301
RAM BACK-UP MODE
The 4519 Group has the RAM back-up mode.
When the EPOF and POF instructions are executed continuously,
system enters the RAM back-up state. The POF instruction is
equal to the NOP instruction when the EPOF instruction is not ex-
ecuted before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM. Table 18 shows the function
and states retained at RAM back-up. Figure 53 shows the state
transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (re-
turn from the normal reset state) can be identified by examining the
state of the RAM back-up flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF and POF instruc-
tions continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
reset pulse is input to RESET pin, or
reset by watchdog timer is performed, or
voltage drop detection circuit detects the voltage drop, or
SRST instruction is executed.
In this case, the P flag is “0.”
Table 18 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Interrupt control registers V1, V2
Interrupt control registers I1, I2
Selection of oscillation circuit
Clock control register MR
Timer 1 function
Timer 2 function
Timer 3 function
Timer 4 function
Watchdog timer function
Timer control register PA, W4
Timer control registers W1 to W3, W5, W6
Serial I/O function
Serial I/O mode register J1
A/D conversion function
A/D control registers Q1 to Q3
Voltage drop detection circuit
Port level
Key-on wakeup control register K0 to K2
Pull-up control registers PU0, PU1
Port output direction registers FR0 to FR3
External 0 interrupt request flag (EXF0)
External 1 interrupt request flag (EXF1)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Timer 3 interrupt request flag (T3F)
Timer 4 interrupt request flag (T4F)
A/D conversion completion flag (ADF)
Serial I/O transmission/reception completion flag
(SIOF)
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
RAM back-up
O
O
(Note 3)
(Note 4)
O
O
O
O (Note 5)
O
(Note 3)
(Note 4)
Notes 1:“O” represents that the function can be retained, and “” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
execute the POF instruction.
5: The valid/invalid of the voltage drop detection circuit can be con-
trolled only by VDCE pin.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34519M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES |
| M34-52 | 制造商:GAMEWELL-FCI 制造商全稱:GAMEWELL-FCI 功能描述:Three-Fold Fire Alarm Boxes and Transmitters |
| M34524EDFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34524M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34524MC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES |
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