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參數(shù)資料
| 型號： | M34519E8FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 24/50頁 |
| 文件大?。?/td> | 1808K |
| 代理商： | M34519E8FP |
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30
9571B–AT42–08/10
AT42QT1111-MU/AT42QT1111-AU
REPEAT_TIME: selects the “repeat” time when “Timed” is selected as the trigger to start key
acquisition. The number entered is a multiple of 16 ms. If “0” is entered, the device will operate
in a continuous “free run” mode; that is, the QT1111 will not sleep after its cycle is completed but
will begin the next key acquisition cycle immediately.
Default KEY_AC value:
1 (timed)
Default MODE value:
0 (7-key mode)
Default SIGNAL value:
1 (parallel)
Default SYNC value:
1 (edge)
Default REPEAT_TIME value:
2 (32 ms cycle)
7.5
Address 1: Guard Key/Comms Options
GUARD_KEY: specifies the key (0 to 10) to be used as a guard channel (see Section 2.3 on
page 7) .
GD_EN: enables the use of a guard key; 0 = disable, 1 = enable.
SPI_EN: enables the Quick SPI interface; 0 = disable, 1 = enable.
See Section 4.1.6 on page 16 for details of the Quick SPI Mode report.
To exit this mode (and clear the “SPI_EN” bit), the command “0x36” should be sent. To save the
settings to EEPROM and make Quick SPI mode active on startup, send the “Store to EEPROM”
command (0x0A). Any other data sent is ignored in Quick SPI mode.
CHG: the CHANGE pin mode (see Section 4.5 on page 18):
0 = “Data” mode. In this mode the “Change” pin is asserted to indicate unread data.
1 = “Touch” mode. In this mode the “Change” pin is asserted when a key is being touched
or is in detect.
CRC: enables or disables CRC; 0 = disable, 1 = enable. When this option is enabled, each data
exchange must have a CRC byte appended.
When report or setup data is being returned by the QT1111, a 1-byte checksum is returned. The
host should confirm that this checksum is correct and, if not, should request the report again.
Where data is being sent by the host, a 1-byte CRC should be sent. The QT1111 returns the
expected CRC byte in the same transaction the CRC byte is sent. In this way, the host can
immediately determine whether the setup data bytes were received correctly.
If the host sends an incorrect CRC following a “Get” command, the QT1111 returns the code
“0xEE” to indicate an error. It then resets the SPI interface. On the next byte exchange 0x55 is
transmitted.
Default GUARD_KEY value:
0 (Key 0)
Default GD_EN value:
0 (disabled)
Default CHG value:
0 (data mode)
Default CRC value:
0 (disabled)
Table 7-3.
Guard Key/Comms Options
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
GUARD_KEY
GD_EN
SPI_EN
CHG
CRC
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相關(guān)代理商/技術(shù)參數(shù) |
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