參數(shù)資料
型號： M34518M4-XXXSP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32
封裝： 8.90 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù)： 50/160頁
文件大小： 1078K
代理商： M34518M4-XXXSP
Skip condition
Datailed description
Carry
flag
CY
Rev.3.01
2005.06.15
page 143 of 157
REJ03B0008-0301
4518 Group
–
V22 = 0: (ADF) = 1
–
(P) = 1
(WDF1) = 1
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,
and the low-order 4 bits (AD3–AD0) of register AD to register A.
(Q13: bit 3 of A/D control register Q1)
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt con-
trol register V2)
Transfers the contents of A/D control register Q1 to register A.
Transfers the contents of register A to A/D control register Q1.
Transfers the contents of A/D control register Q2 to register A.
Transfers the contents of register A to A/D control register Q2.
Transfers the contents of A/D control register Q3 to register A.
Transfers the contents of register A to A/D control register Q3.
No operation; Adds 1 to program counter value, and others remain unchanged.
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
Makes the immediate after POF instruction valid by executing the EPOF instruction.
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
System reset occurs.
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