
Rev.3.01
2005.06.15
page 60 of 157
REJ03B0008-0301
4518 Group
 Port output structure control register FR0 ...........................................................................
 Port output structure control register FR1 ...........................................................................
 Port output structure control register FR2 ...........................................................................
 Carry flag (CY) ......................................................................................................................
 Register A .............................................................................................................................
 Register B .............................................................................................................................
 Register D .............................................................................................................................
 Register E .............................................................................................................................
 Register X .............................................................................................................................
 Register Y .............................................................................................................................
 Register Z .............................................................................................................................
 Stack pointer (SP) ................................................................................................................
 Operation source clock .......................................................... On-chip oscillator (operating)
 Ceramic resonator circuit .............................................................................................. Stop
 RC oscillation circuit ...................................................................................................... Stop
 Quartz-crystal oscillation circuit .................................................................................... Stop
“” represents undefined.
Fig. 50 Internal state at reset 2
00
0
00
00
11
1