參數(shù)資料
型號(hào): M34513M4-070FP
廠商: Mitsubishi Electric Corporation
英文描述: Hook-Up Wire; Conductor Size AWG:28; No. Strands x Strand Size:7 x 36; Jacket Color:Red; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
中文描述: 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù): 38/106頁(yè)
文件大?。?/td> 1304K
代理商: M34513M4-070FP
38
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Table 13 Processing sequence of data transfer from master to slave
Master (transmission)
[Initial setting]
Setting the serial I/O mode register J1 and inter-
rupt control register V2 shown in Figure 24.
TJ1A and TV2A instructions
Setting the port received the reception enable
signal (S
RDY
) to the input mode.
(Port D
5
is used in this example)
SD instruction
* [Transmission enable state]
Storing transmission data to serial I/O register SI.
TSIAB instruction
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally be-
cause serial transfer is performed as long as clock is externally
input. (Unlike an internal clock, an external clock is not stopped
when serial transfer is completed.) However, the SIOF flag is set to
“1” when the clock is counted 8 times after executing the SST in-
struction. Be sure to set the initial level of the external clock to “H.”
[Transmission]
Check port D
5
is “L” level.
SZD instruction
Serial transfer starts.
SST instruction
Check transmission completes.
SNZSI instruction
Wait (timing when continuously transferring)
Slave (reception)
[Initial setting]
Setting serial I/O mode register J1, and interrupt control register V2 shown in
Figure 24.
TJ1A and TV2A instructions
Setting the port received the reception enable signal (S
RDY
) and outputting “H”
level (reception impossible).
(Port D
5
is used in this example)
SD instruction
*[Reception enable state]
The SIOF flag is cleared to “0.”
SST instruction
“L” level (reception possible) is output from port D
5
.
RD instruction
[Reception]
Check reception completes.
SNZSI instruction
“H” level is output from port D
5
.
SD instruction
[Data processing]
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