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參數(shù)資料
| 型號(hào)： | M34513E4 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片4位微機(jī)的CMOS |
| 文件頁數(shù)： | 32/106頁 |
| 文件大?。?/td> | 1304K |
| 代理商： | M34513E4 |
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32
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
(6) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload reg-
ister (R3). Data can be set simultaneously in timer 3 and the reload
register (R3) with the T3AB instruction. Data can be written to re-
load register (R3) with the TR3AB instruction.
When writing data to reload register R3 with the TR3AB instruction,
the downcount after the underflow is started from the setting value
of reload register R3.
Timer 3 starts counting after the following process;
set data in timer 3,
select the count source with the bits 0 and 1 of register W3, and
set the bit 3 of register W3 to “1.”
However, P3
1
/INT1 pin input can be used as the start trigger for
timer 3 count operation by setting the bit 2 of register W3 to “1.”
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 becomes “0”), the timer
3 interrupt request flag (T3F) is set to “1,” new data is loaded from
reload register R3, and count continues (auto-reload function).
When a value set in reload register R3 is n, timer 3 divides the
count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 3 with the TAB3 instruction. When
reading the data, stop the counter and then execute the TAB3 in-
struction. Timer 3 underflow signal divided by 2 can be output from
D
7
/CNTR1 pin.
(7) Timer 4 (interrupt function)
Timer 4 is an 8-bit binary down counter with the timer 4 reload reg-
ister (R4). Data can be set simultaneously in timer 4 and the reload
register (R4) with the T4AB instruction.
Timer 4 starts counting after the following process;
set data in timer 4,
select the count source with the bits 0 and 1 of register W4, and
set the bit 3 of register W4 to “1.”
Once count is started, when timer 4 underflows (the next count
pulse is input after the contents of timer 4 becomes “0”), the timer
4 interrupt request flag (T4F) is set to “1,” new data is loaded from
reload register R4, and count continues (auto-reload function).
When a value set in reload register R4 is n, timer 4 divides the
count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 4 with the TAB4 instruction. When
reading the data, stop the counter and then execute the TAB4 in-
struction. The output from D
7
/CNTR1 pin by timer 4 underflow
signal divided by 2 can be controlled.
(8) Timer I/O pin (D
6
/CNTR0, D
7
/CNTR1)
D
6
/CNTR0 pin has functions to input the timer 2 count source, and
to output the timer 1 and timer 2 underflow signals divided by 2.
D
7
/CNTR1 pin has functions to input the timer 4 count source, and
to output the timer 3 and timer 4 underflow signals divided by 2.
The selection of D
6
/CNTR0 pin function can be controlled with the
bit 0 of register W6. The selection of D
7
/CNTR1 pin function can be
controlled with the bit 2 of register W6.
The following signals can be selected for the CNTR0 output signal
with the bit 1 of register W6.
timer 1 underflow signal divided by 2
the signal of AND operation between timer 1 underflow signal di-
vided by 2 and timer 2 underflow signal divide by 2
The following signals can be selected for the CNTR1 output signal
with the bit 3 of register W6.
timer 3 underflow signal divided by 2
the signal of AND operation between timer 3 underflow signal di-
vided by 2 and timer 4 underflow signal divide by 2
Timer 2 counts the rising waveform of CNTR0 input when the
CNTR0 input is selected as the count source.
Timer 4 counts the rising waveform of CNTR1 input when the
CNTR1 input is selected as the count source.
(9) Timer interrupt request flags (T1F, T2F,
T3F, and T4F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3, and SNZT4).
Use the interrupt control registers V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
(10) Count start synchronization circuit (timer
1, timer 3)
Each timer 1 and timer 3 has the count start synchronization circuit
which synchronize P3
0
/INT0 pin and P3
1
/INT1 pin, respectively,
and can start the timer count operation.
Timer 1 count start synchronization circuit function is selected by
setting the bit 0 of register W1 to “1.” The control by P3
0
/INT0 pin
input can be performed by setting the bit 0 of register I1 to “1.”
P3
0
/INT0 pin input level can be selected by the bit 2 of register I1
as follows;
I1
2
= “0”: The count start synchronizes the “L” level of P3
0
/INT0 pin
I1
2
= “1”: The count start synchronizes the “H” level of P3
0
/INT0 pin
Timer 3 count start synchronization circuit function is selected by
setting the bit 2 of register W3 to “1.” The control by P3
1
/INT1 pin
input can be performed by setting the bit 0 of register I2 to “1.”
P3
1
/INT1 pin input level can be selected by the bit 2 of register I2
as follows;
I2
2
= “0”: The count start synchronizes the “L” level of P3
1
/INT1 pin
I2
2
= “1”: The count start synchronizes the “H” level of P3
1
/INT1 pin
When timer 1 and timer 3 count start synchronization circuits are
used, the count start synchronization circuits are set, the count
source is input to each timer by inputting valid levels to P3
0
/INT0
pin and P3
1
/INT1 pin. Once set, the count start synchronization cir-
cuit is cleared by clearing the bit I1
0
or I2
0
to “0” or reset.
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