
4509 Group
Rev.1.03
2009.07.27
page 49 of 140
REJ03B0147-0103
 Program counter (PC) ..........................................................................................................
Address 0 in page 0 is set to program counter.
 Interrupt enable flag (INTE) ..................................................................................................
 Power down flag (P) .............................................................................................................
 External 0 interrupt request flag (EXF0) ..............................................................................
 Interrupt control register V1 ..................................................................................................
 Interrupt control register V2 ..................................................................................................
 Interrupt control register I1 ...................................................................................................
 Timer 1 interrupt request flag (T1F) .....................................................................................
 Timer 2 interrupt request flag (T2F) .....................................................................................
 Watchdog timer flags (WDF1, WDF2) ..................................................................................
 Watchdog timer enable flag (WEF) ......................................................................................
 Timer control register PA ......................................................................................................
 Timer control register W1 .....................................................................................................
 Timer control register W2 .....................................................................................................
 Timer control register W5 .....................................................................................................
 Timer control register W6 .....................................................................................................
 Clock control register MR .....................................................................................................
 Clock control register RG .....................................................................................................
 Serial interface transmit/receive completion flag (SIOF) .....................................................
 Serial interface control register J1 .......................................................................................
 Serial interface register SI ....................................................................................................
 A/D conversion completion flag (ADF) .................................................................................
 A/D control register Q1 .........................................................................................................
 Successive comparison register AD ....................................................................................
 Comparator register ..............................................................................................................
 Key-on wakeup control register K0 ......................................................................................
 Key-on wakeup control register K1 ......................................................................................
 Key-on wakeup control register K2 ......................................................................................
 Key-on wakeup control register L1 ......................................................................................
 Pull-up control register PU0 .................................................................................................
 Pull-up control register PU1 .................................................................................................
 Pull-up control register PU2 .................................................................................................
 Port output structure control register FR0 ...........................................................................
 Port output structure control register FR1 ...........................................................................
 Port output structure control register FR2 ...........................................................................
 Port output structure control register FR3 ...........................................................................
 Port output structure control register C1 ..............................................................................
 Carry flag (CY) ......................................................................................................................
 Register A .............................................................................................................................
 Register B .............................................................................................................................
 Register D .............................................................................................................................
 Register E .............................................................................................................................
 Register X .............................................................................................................................
 Register Y .............................................................................................................................
 Register Z .............................................................................................................................
 Stack pointer (SP) ................................................................................................................
 Operation source clock .......................................................... On-chip oscillator (operating)
 Ceramic resonator circuit ..................................................................................... Operating
 RC oscillation circuit ...................................................................................................... Stop
“” represents undefined.
Fig. 43 Internal state at reset
(4) Internal state at reset
Figure 43 shows internal state at reset (they are the same after sys-
tem is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 43 are undefined, so set the initial
value to them.
0
000
0
(Interrupt disabled)
0
00
(Interrupt disabled)
00
(Interrupt disabled)
00
0
1
0
(Prescaler stopped)
00
00(Timer 1 stopped)
00
00(Timer 2 stopped)
00
11
01
0
(On-chip oscillator operating)
0
00
(Serial interface port not selected)
0
00
00
0
00
00
11
1