參數(shù)資料
型號(hào)： M34506M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO20
封裝： 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁(yè)數(shù)： 104/114頁(yè)
文件大?。?/td> 836K
代理商： M34506M4-XXXFP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)當(dāng)前第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
(4)
9.2.4
DMA Destination Address Registers ---------------------------------------------------------------------- 9-20
9.2.5
DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21
9.2.6
DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22
9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27
9.3.1
DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27
9.3.2
DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33
9.3.3
Starting DMA ---------------------------------------------------------------------------------------------------- 9-34
9.3.4
DMA Channel Priority ----------------------------------------------------------------------------------------- 9-34
9.3.5
Gaining and Releasing Control of the Internal Bus ---------------------------------------------------- 9-34
9.3.6
Transfer Units --------------------------------------------------------------------------------------------------- 9-35
9.3.7
Transfer Counts ------------------------------------------------------------------------------------------------- 9-35
9.3.8
Address Space -------------------------------------------------------------------------------------------------- 9-35
9.3.9
Transfer Operation --------------------------------------------------------------------------------------------- 9-35
9.3.10
End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37
9.3.11
Each Register Status after Completion of DMA Transfer -------------------------------------------- 9-37
9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------ 9-38
CHAPTER 10 MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2
10.2 Common Units of Multijunction Timers ----------------------------------------------------------------------------- 10-9
10.2.1
MJT Common Unit Register Map -------------------------------------------------------------------------- 10-10
10.2.2
Prescaler Unit -------------------------------------------------------------------------------------------------- 10-12
10.2.3
Clock Bus and Input/Output Event Bus Control Unit ------------------------------------------------- 10-13
10.2.4
Input Processing Control Unit ------------------------------------------------------------------------------ 10-17
10.2.5
Output Flip-flop Control Unit -------------------------------------------------------------------------------- 10-26
10.2.6
Interrupt Control Unit ----------------------------------------------------------------------------------------- 10-35
10.3 TOP (Output-Related 16-Bit Timer) --------------------------------------------------------------------------------- 10-64
10.3.1
Outline of TOP -------------------------------------------------------------------------------------------------- 10-64
10.3.2
Outline of Each Mode of TOP ------------------------------------------------------------------------------- 10-66
10.3.3
TOP Related Register Map ---------------------------------------------------------------------------------- 10-68
10.3.4
TOP Control Registers ---------------------------------------------------------------------------------------- 10-70
10.3.5
TOP Counters (TOP0CT–TOP10CT) --------------------------------------------------------------------- 10-75
10.3.6
TOP Reload Registers (TOP0RL–TOP10RL) ----------------------------------------------------------- 10-76
10.3.7
TOP Correction Registers (TOP0CC–TOP10CC) ----------------------------------------------------- 10-77
10.3.8
TOP Enable Control Registers ------------------------------------------------------------------------------ 10-78
10.3.9
Operation in TOP Single-shot Output Mode (with Correction Function) -------------------------- 10-80
10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) -------------- 10-86
10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) --------------------- 10-91
10.4 TIO (Input/Output-Related 16-Bit Timer) --------------------------------------------------------------------------- 10-94
10.4.1
Outline of TIO --------------------------------------------------------------------------------------------------- 10-94
10.4.2
Outline of Each Mode of TIO -------------------------------------------------------------------------------- 10-96
10.4.3
TIO Related Register Map ----------------------------------------------------------------------------------- 10-99
10.4.4
TIO Control Registers ----------------------------------------------------------------------------------------- 10-101
10.4.5
TIO Counters (TIO0CT–TIO9CT) -------------------------------------------------------------------------- 10-109
10.4.6
TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) --------------------------------------------- 10-110
10.4.7
TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ---------------------------------------------------------- 10-111
10.4.8
TIO Enable Control Registers ------------------------------------------------------------------------------- 10-112
10.4.9
Operation in TIO Measure Free-Run/ Clear Input Modes -------------------------------------------- 10-114
相關(guān)PDF資料
PDF描述
M34506M2-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO20
M34507E4FP 4-BIT, OTPROM, MICROCONTROLLER, PDSO24
M34507M2-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34507M4-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34507M2-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34507E4FP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34507M2-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
M34507M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34508G4FP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34508G4GP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*