參數(shù)資料
型號(hào)： M34501M2-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO20
封裝： 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁(yè)數(shù)： 40/118頁(yè)
文件大?。?/td> 952K
代理商： M34501M2-XXXFP
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Rev.3.01
2005.02.07
page 26 of 112
REJ03B0104-0301
4501 Group
Fig. 22 Timers structure
16-bit timer (WDT)
116
Instruction clock
Q
S
Q
T
D
WDF2
ORCLK
XIN
1/4
1/16
W13
0
1
0
1
W12
Division circuit
divided by 8
divided by 4
divided by 2
P12/CNTR
P12 output
0
1
W60
0
1
W23
(TR1AB)
T1F
T2F
(TAB1)
0
1
W11
W21,W20
11
10
01
00
1/2
0
1
W61
1/2
(T2AB)
(TAB2)
(TAB1)
(TAB2)
(Note 2)
T1ABT1AB
MR3, MR2
00
01
10
11
W10
0
1
Q
R
S
0
1
I12
0
1
I11
P13/INT
(Note 1)
I10
W22
Timer 1 underflow signal
I13
R
Q
R
S
WEF
Reset signal
(Note 5)
DWDT instruction
+
WRST instruction
(Note 4)
R
WDF1
WRST instruction
(Note 3)
Timer 1 (8)
Timer 1
interrupt
Reload register R1 (8)
Register B Register A
Timer 2 (8)
Reload register R2 (8)
Register B Register A
Timer 2
interrupt
Data is set automatically from each reload
register when timer 1 or 2 underflows
(auto-reload function)
Notes 1: Timer 1 count start synchronous circuit is set
by the valid edge of P13/INT pin selected by
bits 1 (I11) and 2 (I12) of register I1.
2: Count source is stopped by clearing to “0.”
3: When the WRST instruction is executed at
WDF1 flag = “1,” WDF1 flag is cleared to “0”
and the next instruction is skipped.
When the WRST instruction is executed at
WDF1 flag = “0,” skip is not executed.
4: When the DWDT and WRST instructions are
executed continuously, WEF flag is cleared to
“0” and reset by watchdog timer is not executed.
5: The WEF flag is set to “1” at system reset or
RAM back-up mode.
Instruction clock
Internal clock
generating circuit
(divided by 3)
Prescaler
One-sided edge
detection circuit
Both edges
detection circuit
Falling
Rising
Clock
generation
circuit
System clock
Timer 1 underflow signal
Timer 2 underflow signal
Reset signal
Watchdog
reset signal
相關(guān)PDF資料
PDF描述
M34501E4FP 4-BIT, OTPROM, MICROCONTROLLER, PDSO20
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