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參數(shù)資料
| 型號： | M34286G2-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20 |
| 文件頁數(shù)： | 6/30頁 |
| 文件大?。?/td> | 516K |
| 代理商： | M34286G2-XXXGP |
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Rev.1.00
Aug 06, 2008
page 12 of 64
REJ03B0251-0100
4286 Group
Fig. 13 Timers structure
(Note 1)
0
1
V10
CARRY
1
0
V11
Reload register R1 (8)
Timer 1 (8)
Register B
Register A
(T1AB)
(TAB1)
(Note 2)
T1F
SNZT1 instruction
Timer 1 underflow signal
(to port CARR)
Register A
Reload control circuit
(TAB2)
V22
Q
R
T
T2F
Register B
(T2AB)
Reload register R2L (8)
Timer 2(8)
Register B
(T2HAB)
Reload register R2H (8)
0
1
V20 (Note 1)
V21
0
1
(TAB2)
(T2AB)
CARRYD
(to port CARR)
T2F
V23
SNZT2
instruction
XIN
D
T
Q
R
V10
Carrier wave output control signal
V12
Port CARR
SCAR instruction
SQ
R
RCAR instruction
CAR flag
CARRY
(to timer 1)
Timer 1 underflow signal
(T2R2L)
(TAB1)
(Note 3)
1/2
Initializing signal
WRST instruction
System reset
INSTCK
(Note 4)
14-bit timer (WDT)
13
0
5
Initializing signal (Note 4)
WDF1 WDF2
Notes 1: Counting is stopped by clearing to “0.”
2: When the T1AB instruction is executed after V10 is set to “1,”
writing is performed only to reload register R1.
3: The data of reload register R2L set with the T2AB instruction
can be also written to timer 2 with the T2R2L instruction.
4: The initializing signal is output at reset or RAM back-up mode.
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