
WAIT CONTROLLER
18
18-14
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
Figure 18.3.8 Read/Write Timing (for Access with Internal 2 Wait State + Strobe Wait)
Read
Read (3 cycles)
CLKOUT
A9–A30
CS0#–CS3#
BHW#, BLW#
DB0–DB15
WAIT#
RD#
"H"
Note 1: For details about the Bus Mode Control Register, see Section 17.2.2, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 18.2.1, "CS Area Wait Control Registers."
Note: Circles in the above diagram indicate the sampling timing.
Internal
2 wait state
(Don't Care)
"H"
(Don't Care)
Write
Write (3 cycles)
CLKOUT
A9–A30
CS0#–CS3#
BHW#, BLW#
DB0–DB15
WAIT#
RD#
"H"
Internal
2 wait state
Bus Mode Control Register (Note 1)
BUSMOD bit = 0 (WR signal separated)
CS Area Wait Control Register (Note 2)
WAIT bit = 0010 (2 wait)
CWAIT bit = 0 (without CS wait)
SWAIT bit = 1 (with strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
"H"
(Don't Care)
18.3 Typical Operation of the Wait Controller