參數(shù)資料
型號(hào)： M32000D4AFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE CHIP 32 BIT CMOS MICROCOMPUTER
中文描述： 單芯片32位CMOS微機(jī)
文件頁(yè)數(shù)： 26/45頁(yè)
文件大小： 535K
代理商： M32000D4AFP
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
26
Master/slave mode
The M32000D4AFP has an M/S (master/slave) pin for multiproces-
sor configuration use.
master mode (M/S = "H")
This is normal operation mode. Set the M/S pin to an "H" level. It is
used when the M32000D4AFP is used as the main CPU in a system.
slave mode (M/S = "L")
This operation mode is for when the M32000D4AFP is used as a
coprocessor. Set the M/S pin to an "L" level. When set to slave mode,
the M32000D4AFP does not start operation even after a reset, until
an interrupt request or the SBI is input. Processing is carried out by
communicating with the master M32000D4AFP, using the two pro-
grammable I/O ports and the external interrupt signal.
D24
D25
D26
D27
D28
D29
D30
D31
LM
lock control register (MLCR) < address: H'FFFF FFF7>
Fig. 26 Lock control register
______
0: HREQ
exclusive
lock mode
___
1: CS exclusive
lock mode
R = 0 ... "0" when reading
W =
... write enabled
R =
W =
: write disabled
... read enabled
<at reset: H'00>
R
0
D
24 - 30
bit name
Not
assigned.
function
W
31
LM
(lock mode)
Coprocessor only configuration example
The slave M32000D4AFP accesses only the internal DRAM and never
the external bus. M/S and HREQ are fixed at the "L" level. The slave
M32000D4AFP executes the instructions that the master
M32000D4AFP downloads to the internal DRAM. The data transfer
request (processing complete) from the slave M32000D4AFP is no-
tified to the master M32000D4AFP by inputting the interrupt request
via the programmable I/O port. The data transaction is carried out
when the master M32000D4AFP accesses the internal DRAM in the
slave M32000D4AFP.
Common bus coprocessor configuration example
In this configuration, the slave M32000D4AFP can also access the
external bus. Communications between the master and slave CPUs
is carried out using the programmable I/O ports and the interrupt
request input.
<coprocessor only configuration>
<common bus coprocessor configuration>
Fig. 27 Master/slave system configuration example
M32000D4AFP
(master)
ROM
ASIC
INT
PP0
M/S
M/S
HREQ
INT
M32000D4AFP
(slave)
no access to
external bus
M32000D4AFP
(master)
ROM
ASIC
PP0
M/S
M/S
HREQ
INT
M32000D4AFP
(slave)
HACK
HREQ
HACK
INT
bus
arbiter
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