參數(shù)資料
型號: M32000D4
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE CHIP 32 BIT CMOS MICROCOMPUTER
中文描述: 單芯片32位CMOS微機(jī)
文件頁數(shù): 40/45頁
文件大?。?/td> 535K
代理商: M32000D4
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4AFP
40
CLKIN
(input)
(output)
(output)
0.5 VCC
(input)
(output)
D0 to D15
D0 to D15
(input)
t
d(CLKIN-DV)
t
d(CLKIN-DZX)
33
t
d(CLKIN-DVX)
t
d(CLKIN-DXZ)
35
t
su(DCL-CLKIN)
t
h(CLKIN-DCL)
t
su(D-CLKIN)
t
h(CLKIN-D)
BS
BCH, BCL
DC
13
15
30
31
32
34
38
39
(output)
A8 to A30
t
d(CLKIN-AV)
16
(output)
t
d(CLKIN-STV)
SID, ST
22
(output)
t
d(CLKIN-RWV)
R/W
24
(output)
BURST
t
d(CLKIN-BSH)
t
d(CLKIN-BURSTL)
27
t
d(CLKIN-BURSTH)
29
t
d(CLKIN-BSL)
t
d(CLKIN-BCV)
18
t
d(CLKIN-SIDV)
20
12
t
d(CLKIN-BSHX)
14
t
d(CLKIN-BSLX)
t
d(CLKIN-AX)
17
t
d(CLKIN-BCX)
19
t
d(CLKIN-STX)
23
t
d(CLKIN-SIDX)
21
t
d(CLKIN-RWX)
25
t
d(CLKIN-BURSTHX)
26
t
d(CLKIN-BURSTLX)
28
t
su(DCH-CLKIN)
t
h(CLKIN-DCH)
36
37
*1 The set up/hold of DC = "H" may vary depending on the wait cycle insertion.
*2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to
the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of
the actual CLKIN is necessary.
[example]
BS signal transition ("L" –> "H") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (
±
5%) to CLKIN:
*1
*1
minimum value of td(CLKIN-BSLX) = (value in table) – (correction value) = 15 – (60 x 5/100) = 12 [ns]
maximum value of td(CLKIN-BSH) = (value in table) + (correction value) = (60/4 + 8) + (60 x 5/100) = 26 [ns]
*2
*2
*2
*2
*2
*2
0.5 VCC
Fig. 40 Read/write timing
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