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16. Serial I/O (Special Function)
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16.4 Special Mode 2
In special mode 2, serial communication between one or multiple masters and multiple slaves is available.
_____
The SSi input pin (i=0 to 4) controls the serial bus communication. Table 16.19 lists specifications of special
mode 2. Table 16.20 lists registers to be used and settings. Tables 16.20 to 16.22 list pin settings.
Table 16.19. Special Mode 2 Specifications
Item
Specification
Transfer Data Format
Transfer data : 8 bits long
Transfer Clock
The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected) : fj/2(m+1)
fj = f1, f8, f2n(1) m : setting value of the UiBRG register
0016 to FF16
The CKDIR bit to "1" (external clock selected) : input clock from the CLKi pin
Transmit/Receive Control
______
SSi input pin function
Transmit Start Condition
To start transmitting, the following requirements must be met(2) :
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Receive Start Condition
To start receiving, the following requirement must be met(2) :
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit to "1" (receive enable)
- Set the TI bit to "0" (data in the UiTB register)
Interrupt Request
Transmit interrupt timing can be selected from the followings:
Generation Timing
- The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) :
when data is transferred from the UiTB register to the UARTi transmit register (transmission
started)
- The UiIRS register is set to "1" (transmission completed):
when data transmission from UARTi transfer register is completed
Receive interrupt timing
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
Error Detection
Overrun error(3)
This error occurs when the seventh bit of the next received data is read before reading the
UiRB register
Fault error
______
In master mode, the fault error occurs an "L" signal is applied to the SSi pin
Selectable Function
CLK polarity
Select from the rising edge or falling edge of the transfer clock when transferred data is output and input
LSB first / MSB first
Data is transmitted or received in either bit 0 or in bit 7
Continuous receive mode
Reception is enabled simultaneously by reading the UiRB register
Serial data logic inverse
This function inverses transmitted or received data logically
TxD, RxD I/O polarity Inverse
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
Clock phase
Select from one of 4 combinations of transfer data polarity and phases
_____
SSi input pin function
Output pin is placed in a high-impedance state to avoid data conflict between master and other
masters or slaves
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit
in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the
rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising
edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L").
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1"
(interrupt requested).