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| 型號： | M30826MH-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 847K |
| 代理商： | M30826MH-XXXGP |
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30024743
FIGURE 13. Single-Ended to Differential Signal
Conversion using a Balun
Figure 13 is a generic depiction of a single-ended to differen-
tial signal conversion using a balun. The circuitry specific to
the balun will depend upon the type of balun selected and the
overall board layout. It is recommended that the system de-
signer contact the manufacturer of the balun they have se-
lected to aid in designing the best performing single-ended to
differential conversion circuit using that particular balun.
When selecting a balun, it is important to understand the input
architecture of the ADC. There are specific balun parameters
of which the system designer should be mindful. A designer
should match the impedance of the analog source to the
ADC08D1520’s on-chip 100
differential input termination
resistor. The range of this input termination resistor is de-
scribed in the Converter Electrical Characteristics as the
specification R
IN.
Also, the phase and amplitude balance are important. The
lowest possible phase and amplitude imbalance is desired
when selecting a balun. The phase imbalance should be no
more than ±2.5° and the amplitude imbalance should be lim-
ited to less than 1dB at the desired input frequency range.
Finally, when selecting a balun, the VSWR (Voltage Standing
Wave Ratio), bandwidth and insertion loss of the balun should
also be considered. The VSWR aids in determining the overall
transmission line termination capability of the balun when in-
terfacing to the ADC input. The insertion loss should be
considered so that the signal at the balun output is within the
specified input range of the ADC as described in the Con-
verter Electrical Characteristics as the specification V
IN.
2.3.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh. Note that
when the device is programmed to provide a second DCLK
output, the OR signals become DCLK2. Refer to 1.4 REGIS-
2.3.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08D1520 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08D1520 such that the differential full-scale
input range at the analog inputs is a normal amplitude with
the FSR pin high, or a reduced amplitude with FSR pin low as
defined by the specification V
IN in the Converter Electrical
Characteristics. Best SNR is obtained with FSR high.
2.4 THE CLOCK INPUTS
The ADC08D1520 has differential LVDS clock inputs, CLK+
and CLK-, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC08D1520 is tested and
its performance is guaranteed with a differential 1.5 GHz
clock, it typically will function well with input clock frequencies
indicated in the Converter Electrical Characteristics. The
clock inputs are internally terminated and biased. The input
clock signal must be capacitive coupled to the clock pins as
indicated in Figure 14.
Operation up to the sample rates indicated in the Converter
Electrical Characteristics is typically possible if the maximum
ambient temperatures indicated are not exceeded. Operating
at higher sample rates than indicated for the given ambient
temperature may result in reduced device reliability and prod-
uct lifetime. This is because of the higher power consumption
and die temperatures at high sample rates. Important also for
reliability is proper thermal management. See 2.7.2 Thermal
30024747
FIGURE 14. Differential (LVDS) Input Clock Connection
The differential input clock line pair should have a character-
istic impedance of 100
and (when using a balun), be termi-
nated at the clock source in that (100
) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1520 clock input is internally
terminated with an untrimmed 100
resistor.
Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high input clock levels could cause a
change in the analog input offset voltage. To avoid these
problems, keep the input clock level within the range specified
in the Converter Electrical Characteristics.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1520 fea-
tures a duty cycle clock correction circuit which can maintain
performance over temperature even in DES Mode. The ADC
will meet its performance specification if the input clock
high and low times are maintained within the range
(20/80% ratio).
High speed, high performance ADCs such as the AD-
C08D1520 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
t
J(MAX) = (VIN(P-P)/VINFSR) x (1/(2
(N+1)
x
π x f
IN))
where t
J(MAX) is the rms total of all jitter sources in seconds,
V
IN(P-P) is the peak-to-peak analog input signal, VINFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and f
IN is the maximum input frequency, in Hertz, at the ADC
analog input.
Note that the maximum jitter described above is the RSS sum
of the jitter from all sources, including that in the ADC input
clock, that added by the system to the ADC input clock and
input signals and that added by the ADC itself. Since the ef-
39
www.national.com
ADC08D1520QML
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30828MH-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER |
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