參數(shù)資料
型號(hào): M30800FCFP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 9/317頁(yè)
文件大?。?/td> 4621K
代理商: M30800FCFP
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deveopmen
Pin Description
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
9
Pin Description
Signal name
Function
Pin name
I/O type
I/O port P5
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Input/output
Input/output
I/O port P6
I/O port P7
I/O port P8
I/O port P8
5
I/O port P9
I/O port P10
P5
0
to P5
7
P6
0
to P6
7
P7
0
to P7
7
P8
0
to P8
4
,
P8
6
,
P8
7
,
P8
5
P9
0
to P9
7
P10
0
to P10
7
This is an 8-bit I/O port equivalent to P0. P5
3
in this port outputs a
divide-by-8 or divide-by-32 clock of X
IN
or a clock of the same
frequency as X
CIN
as selected by software.
Output
Output
Output
Output
Output
Input
Output
Input
This is an 8-bit I/O port equivalent to P0. When set for input in single
chip mode, the user can specify in units of four bits via software
whether or not they are tied to a pull-up resistance. In memory
expansion and microprocessor mode, an built-in pull-up resistance
cannot be used. Pins in this port also function as UART0 and UART1 I/
O pins as selected by software.
This is an 8-bit I/O port equivalent to P6 (P7
0
and P7
1
are N-channel
open drain output). Pins in this port also function as timer A
0
–A
3
,
timer B5 or UART2 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as UART3 and UART4 I/O pins, Timer B0–B4 input pins, D-A converter
output pins, A-D converter extended input pins, or A-D trigger input pins
as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P10
4
–P10
7
also function as
input pins for the key input interrupt function.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
P8
0
to P8
4
, P8
6
, and P8
7
are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8
6
and P8
7
can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8
6
(X
COUT
pin) and P8
7
(X
CIN
pin). P8
5
is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be canceled using
software. The pull-up cannot be set for this pin.
DW,
CASL,
CASH,
RAS
Output
Output
Output
Output
When accessing to DRAM area while DW signal is “L”, write to DRAM.
CASL and CASH show timing when latching to line address. When
CASL accesses to even address, and CASH to odd, these two pins
become “L”. RAS signal shows timing when latching to row address.
P4
0
to P4
7
I/O port P4
This is an 8-bit I/O port equivalent to P0.
Input/output
Output
Output
CS
0
to CS
3
These pins output CS
0
–CS
3
signals. CS
0
–CS
3
are chip select signals
used to specify an access space.
A
16
to A
22
,
A
23
Output
These pins output 8 high-order address bits (A
16
–A
22
, A
23
). Highest
address bit (A
23
) outputs inversely.
MA8 to MA12
If accessing to DRAM area, these pins output data separated in time by
multiplexing.
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