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參數(shù)資料
| 型號： | M306NNMG-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128 |
| 文件頁數(shù)： | 54/72頁 |
| 文件大小： | 649K |
| 代理商： | M306NNMG-XXXGP |
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Rev.2.10
Aug 25, 2006
page 56 of 67
REJ03B0061-0210
M16C/6N Group (M16C/6NL, M16C/6NN)
5. Electric Characteristics
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
(3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
(3)
__________
HLDA output delay time
Symbol
Parameter
Min.
Standard
Unit
Max.
4
0
(NOTE 1)
4
–4
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.43 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
30
25
30
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5
109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5
109
f(BCLK)
– 40 [ns]
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR
ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 k
, hold time of output “L” level is
t = – 30 pF
1 k ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Figure 5.11 Port P0 to P14 Measurement Circuit
DBi
R
C
30 pF
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
NOTE:
1. P11 to P14 are only in the 128-pin version.
Measuring
Condition
Figure 5.11
f(BCLK) is 12.5 MHz or less.
VCC = 3.3 V
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