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    參數(shù)資料
    型號(hào): M306N4FGGP
    元件分類: 微控制器/微處理器
    英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
    封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
    文件頁(yè)數(shù): 9/28頁(yè)
    文件大?。?/td> 844K
    代理商: M306N4FGGP
    Rev.2.40
    Aug 25, 2006
    page 15 of 88
    REJ03B0003-0240
    M16C/6N Group (M16C/6N4)
    4. Special Function Registers (SFRs)
    Under development
    This document is under development and its contents are subject to change.
    4. Special Function Registers (SFRs)
    An SFR (Special Function Register) is a control register for a peripheral function.
    Tables 4.1 to 4.16 list the SFR Information.
    Table 4.1 SFR Information (1)
    (3)
    0000h
    0001h
    0002h
    0003h
    0004h
    0005h
    0006h
    0007h
    0008h
    0009h
    000Ah
    000Bh
    000Ch
    000Dh
    000Eh
    000Fh
    0010h
    0011h
    0012h
    0013h
    0014h
    0015h
    0016h
    0017h
    0018h
    0019h
    001Ah
    001Bh
    001Ch
    001Dh
    001Eh
    001Fh
    0020h
    0021h
    0022h
    0023h
    0024h
    0025h
    0026h
    0027h
    0028h
    0029h
    002Ah
    002Bh
    002Ch
    002Dh
    002Eh
    002Fh
    0030h
    0031h
    0032h
    0033h
    0034h
    0035h
    0036h
    0037h
    0038h
    0039h
    003Ah
    003Bh
    003Ch
    003Dh
    003Eh
    003Fh
    Processor Mode Register 0 (1)
    Processor Mode Register 1
    System Clock Control Register 0
    System Clock Control Register 1
    Chip Select Control Register
    Address Match Interrupt Enable Register
    Protect Register
    Oscillation Stop Detection Register (2)
    Watchdog Timer Start Register
    Watchdog Timer Control Register
    Address Match Interrupt Register 0
    Address Match Interrupt Register 1
    Chip Select Expansion Control Register
    PLL Control Register 0
    Processor Mode Register 2
    DMA0 Source Pointer
    DMA0 Destination Pointer
    DMA0 Transfer Counter
    DMA0 Control Register
    DMA1 Source Pointer
    DMA1 Destination Pointer
    DMA1 Transfer Counter
    DMA1 Control Register
    PM0
    PM1
    CM0
    CM1
    CSR
    AIER
    PRCR
    CM2
    WDTS
    WDC
    RMAD0
    RMAD1
    CSE
    PLC0
    PM2
    SAR0
    DAR0
    TCR0
    DM0CON
    SAR1
    DAR1
    TCR1
    DM1CON
    X: Undefined
    NOTES:
    1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset.
    2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset.
    3. Blank spaces are reserved. No access is allowed.
    Address
    Register
    Symbol
    After Reset
    00000000b (CNVSS pin is "L")
    00000011b (CNVSS pin is "H")
    00001000b
    01001000b
    00100000b
    00000001b
    XXXXXX00b
    XX000000b
    0X000000b
    XXh
    00XXXXXXb
    00h
    X0h
    00h
    X0h
    00h
    0001X010b
    XXX00000b
    XXh
    00000X00b
    XXh
    00000X00b
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