參數(shù)資料
型號： M306H7MG-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 113/115頁
文件大?。?/td> 3146K
代理商： M306H7MG-XXXFP
Rev.2.10
Oct 25, 2006
Page 97 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Figure 10.4
U0MR to U2MR Register and U0C0 to U2C0 Register
UARTi transmit/receive mode register (i=0 to 2)
Symbol
Address
After reset
U0MR to U2MR
03A016, 03A816, 037816
0016
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
RW
CKDIR
SMD1
SMD0
Serial I/O mode select bit
(Note 2)
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock (Note 1)
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I2C mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
b2 b1 b0
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : No reverse
1 : Reverse
Function
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
UARTi transmit/receive control register 0 (i=0 to 2)
Symbol
Address
After reset
U0C0 to U2C0
03A416, 03AC16, 037C16 000010002
b7
b6
b5
b4
b3
b2
b1
b0
Function
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
Data output select bit
(Note 2)
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Must not be set
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60, P64 and P73 can be used as I/O ports)
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
UFORM Transfer format select bit
(Note 3)
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
Bit name
Bit
symbol
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0
register to “0”.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS1/RTS1 can be used when the UCON register’s CLKMD1 bit = “0” (only CLK1 output) and the UCON register’s RCSP bit =
“0” (CTS0/RTS0 not separated).
RW
RO
(Note 3)
(Note 4)
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