
Rev.1.00
2004.03.23
page 199 of 320
M306H3MC-XXXFP/FCFP
2.14.5 Expansion Register
Control Data slice function. Expansion register composition is shown in Table 2.14.4.
DA5
to
DA0
00
16
01
16
02
16
03
16
04
16
05
16
06
16
07
16
08
16
09
16
0A
16
0B
16
0C
16
0D
16
0E
16
0F
16
10
16
11
16
12
16
13
16
14
16
15
16
17
16
18
16
19
16
1A
16
1B
16
1C
16
1D
16
1E
16
1F
16
20
16
21
16
22
16
23
16
24
16
25
16
26
16
27
16
28
16
29
16
2A
16
2B
16
2C
16
2D
16
2E
16
2F
16
30
16
31
16
32
16
33
16
34
16
35
16
36
16
DD15
LN15_OD0
LN15_OD1
LN17_OD0
LN17_OD1
LN15_EV0
LN15_EV1
DIVS1
FLC15
CHK_FLC15
_
__
_
__
_
__
_
__
_
GETPEEK3
DIVS1
FLC15
CHK_FLC15
GETPEEK3
DIVS1
FLC15
CHK_FLC15
GETPEEK3
ADSTART
HM84SEL
DIVV_CK7
SEL_PDEC
HCOUNT15
STB_RES
RMTSEL
EXAOFF
_
DD14
LN14_OD0
LN14_OD1
LN16_OD0
LN16_OD1
LN14_EV0
LN14_EV1
DIVS0
FLC14
CHK_FLC14
GETPEEK2
GETPEEK1
G
ETPEEK0
GETPEEK1
G
ETPEEK0
GETPEEK1
G
ETPEEK0
FRAM
DIVS0
FLC14
CHK_FLC14
GETPEEK2
FRAM
DIVS0
FLC14
CHK_FLC14
GETPEEK2
FRAM
MPAL
DIVV_CK6
HCOUNT14
YUKOU2
DD13
LN13_OD0
LN13_OD1
LN13_EV0
LN13_EV1
SELVCO
FLC13
CHK_FLC13
SELVCO
FLC13
CHK_FLC13
SELVCO
FLC13
CHK_FLC13
NXP
DIVV_CK5
SEL_VPSH
HCOUNT13
YUKOU1
STBY0
DD12
LN12_OD0
LN12_OD1
LN12_EV0
LN12_EV1
FLC12
CHK_FLC12
FLC12
CHK_FLC12
FLC12
CHK_FLC12
HORAX_ON
DIVV_CK4
SEL_PDCH
HCOUNT12
YUKOU0
VERTX
DD8
LN8_OD0
LN8_OD1
LN8_EV0
LN8_EV1
FLC8
CHK_FLC8
GET_HP0
FLC8
CHK_FLC8
GET_HP0
FLC8
CHK_FLC8
GET_HP0
NORMAL
DIVF_CK0
DIV_PDC5
DIV_VPS5
DIVV_CK0
ADON
VPS_VP8
PLSPOS8
PLSNEG8
HCOUNT8
RMTHD0(8)
RMTHD1(8)
HINT_LINE8
HINT0
FLC7
SEKI7
SLS7
FLC7
SEKI7
SLS7
FLC7
SEKI7
SLS7
DD6
LN6_OD0
LN6_OD1
LN16_EV0
LN16_EV1
LN6_EV0
LN6_EV1
FLC6
CHK_FLC6
SEKI6
SLS_HP6
SLS6
FLC6
CHK_FLC6
SEKI6
SLS_HP6
SLS6
FLC6
CHK_FLC6
SEKI6
SLS_HP6
SLS6
SELSEP0
PDC_VCO_ON
SEPV0
DIV_FSC6
DIV_PDC3
DIV_VPS3
DIVP_CK6
VPS_VP6
PLSPOS6
PLSNEG6
HCOUNT6
RMTHD0(6)
RMTHD1(6)
HINT_LINE6
INTRMT2
DD4
LN4_OD0
LN4_OD1
LN4_EV0
LN4_EV1
FLC4
CHK_FLC4
SEKI4
SLS_HP4
SLS4
FLC4
CHK_FLC4
SEKI4
SLS_HP4
SLS4
FLC4
CHK_FLC4
SEKI4
SLS_HP4
SLS4
FLD1V
SELXT1
DIV_FSC4
DIV_PDC1
DIV_VPS1
SLION_TIM
DIVP_CK4
VPS_VP4
PLSPOS4
PLSNEG4
HCOUNT4
RMTHD0(4)
RMTHD1(4)
HINT_LINE4
INTRMT0
DD3
LN3_OD0
LN3_OD1
LN3_EV0
LN3_EV1
FLC3
CHK_FLC3
SEKI3
SLS_HP3
SLS3
FLC3
CHK_FLC3
SEKI3
SLS_HP3
SLS3
FLC3
CHK_FLC3
SEKI3
SLS_HP3
SLS3
XTAL_VCO
SELXT0
DIV_FSC3
DIV_PDC0
DIV_VPS0
REG_FLD2V
DIVP_CK3
6BITOFF
VPS_VP3
PLSPOS3
PLSNEG3
HCOUNT3
RMTHD0(3)
RMTHD1(3)
HINT_LINE3
VINT3
DD2
LN2_OD0
LN2_OD1
LN2_EV0
LN2_EV1
FLC2
CHK_FLC2
SEKI2
SLS_HP2
SLS2
FLC2
CHK_FLC2
SEKI2
SLS_HP2
SLS2
FLC2
CHK_FLC2
SEKI2
SLS_HP2
SLS2
DIV_FSC2
DIV_PDCS2
DIV_VPSS2
REG_FLD1V
DIVP_CK2
VPS_VP2
PLSPOS2
PLSNEG2
HCOUNT2
RMTHD0(2)
RMTHD1(2)
HINT_LINE2
VINT2
DD1
LN1_OD0
LN1_OD1
LN1_EV0
LN1_EV1
FLC1
CHK_FLC1
SEKI1
SLS_HP1
SLS1
FLC1
CHK_FLC1
SEKI1
SLS_HP1
SLS1
FLC1
CHK_FLC1
SEKI1
SLS_HP1
SLS1
DIV_FSC1
DIV_PDCS1
DIV_VPSS1
ADON_TIM
DIVP_CK1
START
VPS_VP1
PLSPOS1
PLSNEG1
HCOUNT1
RMTHD0(1)
RMTHD1(1)
HINT_LINE1
VINT1
DD0
LN0_OD0
LN0_OD1
LN0_EV0
LN0_EV1
FLC0
CHK_FLC0
SEKI0
SLS_HP0
SLS0
FLC0
CHK_FLC0
SEKI0
SLS_HP0
SLS0
FLC0
CHK_FLC0
SEKI0
SLS_HP0
SLS0
DIV_FSC0
DIV_PDCS0
DIV_VPSS0
ADSEL
DIVP_CK0
ADLAT
VPS_VP0
PLSPOS0
PLSNEG0
HCOUNT0
RMTHD0(0)
RMTHD1(0)
HINT_LINE0
VINT0
Remarks
for
read
for
read
for
read
Line
register
Status
register
1
Status
register
2
Status
register
3
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
___
__
_
__
_
__
_
___
__
_
__
_
SLSLVL
_
___
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
___
_
___
_
DD11
LN11_OD0
LN11_OD1
LN11_EV0
LN11_EV1
FLC11
CHK_FLC11
BIFON
FLC11
CHK_FLC11
BIFON
FLC11
CHK_FLC11
BIFON
DIVF_CK3
DIV_PDC8
DIV_VPS8
DIVV_CK3
STBSYNCSEP
HCOUNT11
STBY1
HINT3
JSTCKON
DD10
LN10_OD0
LN10_OD1
LN10_EV0
LN10_EV1
FLC10
CHK_FLC10
_
SLSLVL
_
SLSLVL
_
FLC10
CHK_FLC10
FLC10
CHK_FLC10
DIVF_CK2
DIV_PDC7
DIV_VPS7
DIVV_CK2
INTDA
SYNCSEP_ON0
HCOUNT10
FILDIV1
PTD8
HINT2
JSTCKDIV1
DD9
LN9_OD0
LN9_OD1
LN9_EV0
LN9_EV1
FLC9
CHK_FLC9
GET_HP1
FLC9
CHK_FLC9
GET_HP1
FLC9
CHK_FLC9
GET_HP1
VPS_VCO_ON
PDC_VCO_R1
P
DC_VCO_R0
DIVF_CK1
DIV_PDC6
DIV_VPS6
DIVV_CK1
INTAD
SLI_GO
HCOUNT9
FILDIV0
PTC8
HINT1
JSTCKDIV0
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
DD5
LN5_OD0
LN5_OD1
LN5_EV0
LN5_EV1
FLC5
CHK_FLC5
SEKI5
SLS_HP5
SLS5
FLC5
CHK_FLC5
SEKI5
SLS_HP5
SLS5
FLC5
CHK_FLC5
SEKI5
SLS_HP5
SLS5
SELXT2
DIV_FSC5
DIV_PDC2
DIV_VPS2
DIVP_CK5
VPS_VP5
PLSPOS5
PLSNEG5
HCOUNT5
RMTHD0(5)
RMTHD1(5)
HINT_LINE5
INTRMT1
_
__
_
DD7
LN7_OD0
LN7_OD1
LN17_EV0
LN17_EV1
LN7_EV0
LN7_EV1
CHK_FLC7
SLS_HP7
CHK_FLC7
SLS_HP7
CHK_FLC7
SLS_HP7
MACRO_ON
DIV_FSC7
DIV_PDC4
DIV_VPS4
DIVP_CK7
VPS_VP7
MASK7
MASK6
MASK5
MASK4
M
ASK3
MASK2
M
ASK1
MASK0
PLSPOS7
PLSNEG7
HCOUNT7
RMTHD0(7)
RMTHD1(7)
HINT_LINE7
INTRMT3
_
__
_
Table 2.14.4 Expansion register composition