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參數(shù)資料
| 型號： | M306H3FCFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116 |
| 封裝： | 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116 |
| 文件頁數(shù)： | 98/135頁 |
| 文件大?。?/td> | 2583K |
| 代理商： | M306H3FCFP |
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Rev.1.00
2004.03.23
page 65 of 320
M306H3MC-XXXFP/FCFP
2.7.6 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 2.7.4 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not re-
quested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
temporary register(Note 1).
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The CPU’s internal temporary register (Note 1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
Indeterminate (Note 1)
1
2
34
56
78
9
10
11
12
13
1415
16
1718
Indeterminate (Note 1)
SP-2
contents
SP-4
contents
vec
contents
vec+2
contents
Interrupt
information
Address
000016
Indeterminate (Note 1)
SP-2
SP-4
vec
vec+2
PC
CPU clock
Address bus
Data bus
WR
RD
Note 1 : The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
Note 2 : The WR signal timing shown here is for the case where the stack is located in the internal RAM.
(Note 2)
Figure 2.7.4. Time Required for Executing Interrupt Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M306H3FCFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 128KB FLASH 5V 116LQFP - Trays |
| M306H3MC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER |
| M306H5FGFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER |
| M306H5FGFP#U0 | 功能描述:IC M16C/6H MCU FLASH 116LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:M16C™ M16C/60 標(biāo)準(zhǔn)包裝:160 系列:S08 核心處理器:S08 芯體尺寸:8-位 速度:40MHz 連通性:I²C，LIN，SCI，SPI 外圍設(shè)備:LCD，LVD，POR，PWM，WDT 輸入/輸出數(shù):53 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1.9K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 12x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:64-LQFP 包裝:托盤 |
| M306H5MC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER |
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